基于漏极导通区特性理解MOSFET开关过程

本文先介绍了基于功率MOSFET的栅极电荷特性的开关过程;然后介绍了一种更直观明析的理解功率MOSFET开关过程的方法:基于功率MOSFET的导通区特性的开关过程,并详细阐述了其开关过程.开关过程中,功率MOSFET动态的经过是关断区、恒流区和可变电阻区的过程.在跨越恒流区时,功率MOSFET漏极的电流和栅极电压以跨导为正比例系列,线性增加.米勒平台区对应着最大的负载电流.可变电阻区功率MOSFET漏极减小到额定的值.     

基于固体开关器件的“过”驱动技术研究

为了提高功率MOSFET的开关速度,从功率MOSFET的开关机理加以分析,通过用仿真与电路实验相结合的方法,研究出了功率MOSFET栅极的“过”驱动技术,大大加快了功率MOSFET的开关速度。     

大功率开关电源中功率MOSFET的驱动技术

功率MOSFET具有导通电阻低、负载电流大的优点，因而非常适合用作开关电源（switch-mode power supplies，SMPS）的整流组件，不过，在选用MOSFET时有一些注意事项。功率MOSFET和双极型晶体管不同，它的栅极电容比较大，在导通之前要先对该电容充电，当电容电压超过阈值电压（VGS-TH）时MOSFET才开始导通。因此，栅极驱动器的负载能力必须足够大，以保证在系统要求的时间内完成对等效栅极电容（CEI）的充电。在计算栅极驱动电流时，最常犯的一个错误就是将MOSFET的输入电容（CISS）和CEI混为一谈，于是会使用下面这个公…     

隔离式MOSFET驱动器IC功效在轻载时得到改善

许多现代功率MOSFET在5V时达到导通电阻的低值,甚至在栅极到源极电压为5V的情况下也可达到。然而．对于大功率MOSFET．特别是绝缘栅极双极晶体管（IGBT）．工程师更希望栅极到源极电压为12V-15V．因为这些电源开关的导通电阻在高栅极到源极电压情况下会进一步降低。     

电源

凌力尔特推出微功率升压型转换器LT8410/-1；Intersil推出极高轻负载效率的MOSFET栅极驱动器；Diodes新型功率MOSFET优化低压操作     

Intersil推出MOSFET栅极驱动器ISL6615和ISL6615A

Intersil推出高频6A吸入电流同步MOSFET栅极驱动器ISL6615和ISL6615A,有助于为系统安全提供更高效率、灵活性和更多保护功能。新型驱动器增加了栅极驱动电流,可以缩短栅极电压上升、下降时间。这大限度地降低开关损耗并改善效率,尤其是在每相并联功率MOSFET的大电流应用当中。利用防止过充电的自举电容器、     

Vishay Siliconix推出首款TrenchFET功率MOSFET

Vishay Intertechnology,Inc.宣布,推出采用针对更高电压器件优化的新型低导通电阻技术的首款TrenchFET(?)功率MOSFET—ThunderFET~(TM)SiR880DP。新器件是业界首款在4.5V栅极驱动下就能导通的80V功率MOSFET。新的80VSiR880DP采用热增强型PowerPAK(?)SO-8封装,在4.5V、7.5V和10V下具有8.5 mΩ、6.7 mΩ和5.9 mΩ的超低导通电阻。在4.5 V栅极驱动下,该器件的典型导通电阻与栅极电荷的乘积为161,该数值是DC-DC转换器应用中MOSFET的优     

基于栅极限流的SiC MOSFET栅电荷测试方案

SiC MOSFET是一种高性能的电力电子器件,其开通/关断过程中积累/释放的栅电荷Q_g对MOSFET的开关速度、功率损耗等参数有重要影响。通常采用在栅极设置恒流源驱动,对时间进行积分的方法来测量Q_g。为了降低驱动复杂度,提高测试结果精度和可视性,基于双脉冲测试平台的感性负载回路,改用耗尽型MOSFET限制栅极电流实现恒流充电,对SiC MOSFET进行测试。同时利用反馈电阻将较小的栅极电流信号转换为较大的电压信号。实验结果表明：在误差允许范围(±5%)内该测试方案能较为准确地测得SiC MOSFET的Q_g,测试结果符合器件规格书曲线。     

具有极低导通电阻的20V N通道功率MOSFET

SiR440DP系列功率MOSFET在20V额定电压时具有低导通电阻及导通电阻与栅极电荷乘积,在4．5V栅极驱动时最大导通电阻为2．0mΩ,在10V栅极驱动时最大导通电阻为1．55mΩ。导通电阻与栅极电荷乘积是DC／DC转换器应用中MOSFET的关键优值（FOM）,在4．5V时为87。SiR440DP将在同步降压转换器以及二级同步整流及OR—ing应用中用作低端MOSFET。其低传导及切换损耗将确保稳压器模块（VRM）、服务器及使用负载点（POL）功率转换的诸多系统实现功效更高且更节省空间的设计。     

焦点产品

PowerTrench~(TM)系列功率MOSFET 快捷(Fairchild)半导体推出一种PowerTrench技术制造的功率MOSFET,据美国快捷半导体香港有限公司市务经理郭耀明介绍,与平面工艺相比,用PowerTrench技术制造的功率MOSFET 电流大,而且导通电阻较低和栅极充电电荷较小。例如,NDS8410A是用平面工艺制造的,同一档的FDS6690A是用PowerTrench工艺制造的。前者的导通电阻是12mΩ和后者的13.5mΩ相近;但是,在栅源电压为10 V时,前者的栅极充电电容是45nC,后者仅有29nC。     

SEGR- and SEB-hardened structure with DSPSOI in power MOSFETs

Single event irradiation-hardened power MOSFET is the most important device for DC/DC converter in space environment application.Single event gate rupture (SEGR) and single event burnout (SEB),which will degrade the running safety and reliability of spacecraft,are the two typical failure modes in power MOSFETs.In this paper,based on recombination mechanism of interface between oxide and silicon,a novel hardened power MOSFETs structure for SEGR and SEB is proposed.The structure comprises double stagger partial silicon-on-insulator (DSPSOI) layers.Results show that the safety operation area (SOA) of a 130 V N-channel power MOSFET in single event irradiation environment is enhanced by up to 50％ when the linear-energy-transfer value of heavy ion is a constant of 98 MeV.cm2/mg in the whole incident track,and the other parameters are almost maintained at the same value.Thus this novel structure can be widely used in designing single event irradiation-hardened power MOSFETs.     

Measurement of a cross-section for single-event gate rupture inpower MOSFETs

The heavy-ion fluence required to induce Single-Event Gate Rupture (SEGR) in power MOSFETs is measured as a function of the drain bias, V _DS, and as a function of the gate bias, V_GS. These experiments reveal the abrupt nature of the SEGR-voltage threshold. In addition, the concepts of cross-section, threshold, and saturation in the SEGR phenomenon are introduced. This experimental technique provides a convenient method to quantify heavy-ion effects in power MOSFETs     

国产中高压抗辐照功率MOSFET单粒子效应

功率金属-氧化物半导体场效应晶体管(MOSFET)空间使用时易遭受重离子轰击产生单粒子效应(单粒子烧毁和单粒子栅穿)。本文对国产新型中、高压(额定电压250 V,500 V)抗辐照功率MOSFET的单粒子辐射效应进行了研究,并采取了有针对性的加固措施,使器件的抗单粒子能力显著提升。结果表明：对250 V KW2型功率MOSFET器件进行Bi粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到250 V;对500 V KW5型功率MOSFET器件进行Xe粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到400 V,并且当栅压为-15 V时,安全工作的漏极电压也达到400 V,说明国产中、高压功率MOSFET器件有较好的抗单粒子能力。     

功率VDMOS器件的SEB致SEGR效应研究

功率VDMOS器件是航天器电源系统配套的核心元器件之一,在重粒子辐射下会发生单粒子烧毁(SEB)和单粒子栅穿(SEGR)效应,严重影响航天器的在轨安全运行。本文在深入分析其单粒子损伤机制及微观过程的基础上,发现了功率VDMOS器件在重粒子辐射下存在SEBIGR效应,并在TCAD软件和¹⁸¹Ta粒子辐射试验中进行了验证。引起该效应的物理机制是,重粒子触发寄生三极管,产生瞬时大电流,使得硅晶格温度升高,高温引起栅介质层本征击穿电压降低,继而触发SEGR效应。SEBIGR效应的发现为深入分析功率MOSFET器件的单粒子辐射效应奠定了理论基础。     

Impact of the gate driver voltage on temperature sensitive electrical parameters for condition monitoring of SiC power MOSFETs

Condition monitoring using temperature sensitive electrical parameters (TSEPs) is widely recognized as an enabler for health management of power modules. The on-state resistance/forward voltage of MOSFETs, IGBTs and diodes has already been identified as TSEPs by several researchers. However, for SiC MOSFETs, the temperature sensitivity of on-state voltage/resistance varies depending on the device and is generally not as high as in silicon devices. Recently the turn-on current switching rate has been identified as a TSEP in SiC MOSFETs, but its temperature sensitivity was shown to be significantly affected by the gate resistance. Hence, an important consideration regarding the use of TSEPs for health monitoring is how the gate driver can be used for improving the temperature sensitivity of determined electrical parameters and implementing more effective condition monitoring strategies. This paper characterizes the impact of the gate driver voltage on the temperature sensitivity of the on-state resistance and current switching rate of SiC power MOSFETs. It is shown that the temperature sensitivity of the switching rate in SiC MOSFETs increases if the devices are driven at lower gate voltages. It is also shown, that depending on the SiC MOSFET technology, reducing the gate drive voltage can increase the temperature sensitivity of the on-state resistance. Hence, using an intelligent gate driver with the capability of customizing occasional switching pulses for junction temperature sensing using TSEPs, it would be possible to implement condition monitoring more effectively for SiC power devices.     

Gate-resistance-limited switching frequencies of power MOSFETs

High-frequency switching limitation of a power MOSFET resulting from large gate resistance is studied. It is shown that a maximum gate switching frequency can be identified to minimize resistive power dissipation in the gate. Power MOSFETs with refractory silicide gates are shown to result in more than a fivefold improvement in this frequency compared to conventional heavily POCl₃-doped polysilicon-gated MOSFETs with metal gate runners     

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recyclinginput/output buffers

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V_th) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V_th MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V_th MOSFETs, which are cut off during standby. The high-V_th, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words×16-bits SRAM test chip, which was fabricated with a 0.5-μm multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 μW, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads     

Resonant gate driver with efficient gate energy recovery and switching loss reduction

This article describes a novel resonant gate driver for charging the gate capacitor of power metal-oxide semiconductor field-effect-transistors (MOSFETs) that operate at a high switching frequency in power converters. The proposed resonant gate driver is designed with three small MOSFETs to build up the inductor current in addition to an inductor for temporary energy storage. The proposed resonant gate driver recovers the CV² gate loss, which is the largest loss dissipated in the gate resistance in conventional gate drivers. In addition, the switching loss is reduced at the instants of turn on and turn off in the power MOSFETs of power converters by using the proposed gate driver. Mathematical analyses of the total loss appearing in the gate driver circuit and the switching loss reduction in the power switch of power converters are discussed. Finally, the proposed resonant gate driver is verified with experimental results at a switching frequency of 1 MHz.     

The future of power semiconductor device technology

Power electronic systems have benefited greatly during the past ten years from the revolutionary advances that have occurred in power discrete devices. The introduction of power metal-oxide-semiconductor field-effect transistors (MOSFETs) in the 1970s and the insulated gate bipolar transistors (IGBTs) in the 1980s enabled design of very compact high-efficiency systems due to the greatly enhanced power gain resulting from the high input impedance of these structures. Recently, significant improvements in the performance of silicon-power MOSFETs has been achieved by using innovative vertical structures with charge coupled regions. Meanwhile, silicon IGBTs continue to dominate the medium- and high-voltage application space sue to scaling of their voltage ratings and refinements to their gate structure achieved by using very large scale integration (VLSI) technology and trench gate regions. Research on a variety of MOS-gated thyristors has also been conducted, resulting in some promising improvements in the tradeoff between on-state power loss, switching power loss, and the safe-operating-area. Concurrent improvements in power rectifiers have been achieved at low-voltage ratings using Schottky rectifier structures containing trenches and at high-voltage ratings using structures that combine junction and Schottky barrier contacts. On the longer term, silicon carbide Schottky rectifiers and power MOSFETs offer at least another tenfold improvement in performance. Although the projected performance enhancements have been experimentally demonstrated, the defect density and cost of the starting material are determining the pace of commercialization of this technology at present     

Short-channel modeling of bulk accumulation MOSFETs

Physically based short-channel effect (SCE) models are derived for bulk accumulation MOSFETs. Using the proposed models, threshold voltage rolloff, subthreshold swing, and subthreshold current can be accurately calculated; this enables physical insights into device scaling behavior, and prediction of scaling limits. The models enable optimization of accumulation MOSFETs, resulting in small SCE, and low process sensitivity. The models are equally applicable to inversion MOSFETs, and allow easy comparison between accumulation and inversion MOSFETs. Novel application areas of accumulation MOSFETs are identified where they perform better than inversion MOSFETs (better on-current and lower SCE for a given off-current). With mid-band metal gate, accumulation MOSFETs perform better than inversion MOSFETs in ultra low power applications. For poly gate CMOS, accumulation MOSFETs perform better than inversion MOSFETs in low standby power applications.