亚0.1μm高K栅介质MOSFETs的特性

用二维模拟软件 ISE研究了典型的 70 nm高 K介质 MOSFETs的短沟性能 .结果表明 ,由于 FIBL 效应 ,随着栅介质介电常数的增大 ,阈值电区减小 ,而漏电流和亚阈值摆幅增大 ,导致器件短沟性能退化 .这种退化可以通过改变侧墙材料来抑制     

注F短沟MOSFET的抗热载流子损伤特性

研究了用注 F工艺制作的短沟 MOSFET的热载流子效应。实验结果表明 ,在栅介质中注入适量的 F能够明显地减小由热载流子注入引起的阈电压漂移、跨导退化和输出特性的变化。分析讨论了 F的抗热载流子损伤的机理     

硼扩散引起薄SiO2栅介质的性能退化

采用表沟p+多晶硅栅/PMOSFET代替埋沟n+多晶硅栅/PMOSFET具有易于调节阈值电压、降低短沟效应和提高器件开关特性的优点,因而在深亚微米CMOS工艺中被采纳.但是多晶硅掺杂后的高温工艺过程会使硼杂质扩散到薄栅介质和沟道区内,引起阈值电压不稳定和栅介质击穿性能变差.迄今为止对硼扩散退化薄栅介质可靠性的认识并不是很明朗,为此本文考察了硼扩散对薄栅介质击穿电荷和Fowler-Nordheim (FN)电应力产生SiO2/Si界面态的影响.     

氮注入多晶硅栅对超薄SiO2栅介质性能的影响

p+多晶硅栅中的硼在SiO2栅介质中的扩散会引起栅介质可靠性退化,在多晶硅栅内注入N+的工艺可抑制硼扩散.制备出栅介质厚度为4.6nm的p+栅MOS电容,通过SIMS测试分析和I-V、C-V特性及电应力下击穿特性的测试,观察了多晶硅栅中注N+工艺对栅介质性能的影响.实验结果表明:在多晶硅栅中注入氮可以有效抑制硼扩散,降低了低场漏电和平带电压的漂移,改善了栅介质的击穿性能,但同时使多晶硅耗尽效应增强、方块电阻增大,需要折衷优化设计.     

氮注入多晶硅栅对超薄SiO_2栅介质性能的影响

p+ 多晶硅栅中的硼在 Si O2 栅介质中的扩散会引起栅介质可靠性退化 ,在多晶硅栅内注入 N+ 的工艺可抑制硼扩散 .制备出栅介质厚度为 4 .6 nm的 p+栅 MOS电容 ,通过 SIMS测试分析和 I- V、C- V特性及电应力下击穿特性的测试 ,观察了多晶硅栅中注 N+工艺对栅介质性能的影响 .实验结果表明 :在多晶硅栅中注入氮可以有效抑制硼扩散 ,降低了低场漏电和平带电压的漂移 ,改善了栅介质的击穿性能 ,但同时使多晶硅耗尽效应增强、方块电阻增大 ,需要折衷优化设计 .     

50nm SOI-DTMOS器件的性能

利用二维器件模拟软件ISE对50nm沟道长度下SOI-DTMOS器件性能进行了研究,并与常规结构的SOI器件作了比较.结果表明,在50nm沟长下,SOI-DTMOS器件性能远远优于常规SOI器件.SOI-DTMOS器件具有更好的亚阈值特性,其亚阈值泄漏电流比常规SOI器件小2～3个数量级,从而使其具有更低的静态功耗.同时,SOI-DTMOS器件较高的驱动电流保证了管子的工作速度,并且较常规SOI器件能更有效地抑制短沟道器件的穿通效应、DIBL及SCE效应,从而保证了在尺寸进一步减小的情况下管子的性能.对SOI-DTMOS器件的物理机制进行了初步分析,揭示了其性能远优于常规结构的物理本质,同时也指出了进一步研究的方向.     

HALO结构pMOSFETs在V_g=V_d/2应力模式下应力相关的热载流子退化

研究了超薄栅(2 .5 nm )短沟HAL O- p MOSFETs在Vg=Vd/ 2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证     

50nm SOI-DTMOS器件的性能

利用二维器件模拟软件ISE对5 0nm沟道长度下SOI DTMOS器件性能进行了研究,并与常规结构的SOI器件作了比较.结果表明,在5 0nm沟长下,SOI DTMOS器件性能远远优于常规SOI器件.SOI DTMOS器件具有更好的亚阈值特性,其亚阈值泄漏电流比常规SOI器件小2～3个数量级,从而使其具有更低的静态功耗.同时,SOI DTMOS器件较高的驱动电流保证了管子的工作速度,并且较常规SOI器件能更有效地抑制短沟道器件的穿通效应、DIBL及SCE效应,从而保证了在尺寸进一步减小的情况下管子的性能.对SOI DTMOS器件的物理机制进行了初步分析,揭示了其性能远优于常规结构的物理本质     

HALO结构pMOSFETs在Vg=Vd/2应力模式下应力相关的热载流子退化

研究了超薄栅(2.5nm)短沟HALO-pMOSFETs在Vg=Vd/2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证.     

注F短沟MOSFET的沟道热载流子效应

通过对短沟 NMOSFET的沟道热载流子效应研究 ,发现在短沟 NMOSFET栅介质中引入 F离子能明显抑制因沟道热载流子注入引起的阈电压正向漂移和跨导下降以及输出特性曲线的下移 .分析讨论了 F抑制沟道热载流子损伤的机理 . Si— F键释放了 Si/Si O2 界面应力 ,并部分替换了 Si— H弱键是抑制热载流子损伤的主要原因 .     

Short-channel effects in subquarter-micrometer-gate HEMTs:simulation and experiment

The authors studied the electrical properties of subquarter-micrometer-gate HEMTs (high electron mobility transistors) by Monte Carlo simulation and experiment. Simulation shows that subquarter-micrometer-gate HEMTs have extremely high performance, and the near-ballistic movement under the gate was confirmed. It is also shown that the aspect ratio of the channel could be used as a guide to determine the extent of short-channel effects. The transverse-domain formation inherent in short-channel HEMTs may also contribute to the smaller short-channel effect by limiting undesirable substrate current. Experimentally, only a negligible short-channel effect was observed when the gate length was reduced from 1.25 to 0.14 μm. Thus it is not necessary to design and fabricate a special structure for HEMTs, as such a structure might have limited applications     

Short-channel C-MOS/SOS technology

Design, fabrication, and characterization of Si-gate short-channel C-MOS/SOS devices with channel length ranging from 1 to 3 µm are presented. Basic device parameters and their interrelations are discussed and illustrated in detail. Extremely-high-speed and low-power capability has been demonstrated for short-channel devices operating from a 5-V supply voltage. The process reproducibility and circuit performance point to the suitability of short-channel C-MOS/SOS technology for VLSI applications.     

Short-Channel Effect Limitations on High-Frequency Operation of AlGaN/GaN HEMTs for T-Gate Devices

AlGaN/GaN high-electron mobility transistors (HEMTs) were fabricated on SiC substrates with epitaxial layers grown by multiple suppliers and methods. Devices with gate lengths varying from 0.50 to 0.09 mum were fabricated on each sample. We demonstrate the impact of varying the gate lengths and show that the unity current gain frequency response (f_T) is limited by short-channel effects for all samples measured. We present an empirically based physical model that can predict the expected extrinsic f_T for many combinations of gate length and commonly used barrier layer thickness (t_bar) on silicon nitride passivated T-gated AlGaN/GaN HEMTs. The result is that even typical high-aspect-ratio (gate length to barrier thickness) devices show device performance limitations due to short-channel effects. We present the design tradeoffs and show the parameter space required to achieve optimal frequency performance for GaN technology. These design rules differ from the traditional GaAs technology by requiring a significantly higher aspect ratio to mitigate the short-channel effects.     

0.3-μm advanced SAINT FET's having asymmetricn+-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave performance and noise performance of buried p-layer self-aligned gate (BP-SAINT) FETs are discussed. Specifically, a self-aligned gate electrode and an asymmetric n⁺ -layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n⁺-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3-μm gate-length FET was realized without an increase of short-channel effects by using an asymmetric n⁺-layer structure (advanced SAINT). Improvement of microwave performance is confirmed in this FET structure     

Study of the effects of a stepped doping profile in short-channelMOSFETs

The performance of a stepped doping profile for improving the short-channel behavior of a submicrometer MOSFET has been analyzed in detail by using a quasi-two-dimensional (quasi-2-D) MOSFET simulator including inversion-layer quantization coupled with a one-electron Monte Carlo simulation. Several second-order effects, such as mobility degradation both by bulk-impurity and interface traps, carrier-velocity saturation, and channel-length modulation, have been included in the simulator. Very good agreement between experimental and simulated results is obtained for short-channel transistors. It has been shown that including a low-doped zone of convenient thickness next to the interface over a high doping substrate improves both the electron mobility and the threshold voltage of the device, while avoiding short-channel effects. The use of simulation has allowed us to study certain kinds of devices without needing to make them     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Two-dimensional simulation of orientation effects in self-alignedGaAs MESFETs

The stress-induced orientation effects in self-aligned GaAs MESFETs were studied using a two-dimensional analysis. Devices oriented along different crystal directions, with different gate lengths, and under different stress conditions were studied. It was found that the piezoelectric effect caused by the surface stress plays a very important role in the device characteristics of short-channel self-aligned MESFETs. Structure parameters such as lateral spreading of N⁺ ions and p-type impurity concentration in the substrate were found to have great influence on the short-channel effect as well as the orientation effect. The short-channel effects can be suppressed and the device performance improved if the devices are oriented in the right direction and the structure of the devices and the thickness of the surface dielectric layer are properly chosen     

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

An original blocking technology is proposed for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs). In particular, two types of modified devices called poly-Si TFT with block oxide and poly-Si on partial insulator (POPI)-TFT are designed for the first time in this field to enhance device performance. The proposed TFT structures can significantly reduce short-channel effects when compared with a thick source/drain (S/D) poly-Si TFT (i.e., the fully depleted TFT). In addition, an ultrathin (UT) S/D structure (UT-TFT) is designed to verify that the block oxide TFT devices do achieve improved performance without needing the thin active layers and ultrashallow junction depth. Also, the POPI-TFT is found to reduce the thermal instability through its natural body-tied scheme.     

Current gain high-frequency CMOS operational amplifiers

The performance of high unity gain-bandwidth current gain-based CMOS operational amplifiers fabricated in a 1.5-/spl mu/m CMOS digital process is discussed. High unity-gain bandwidth was achieved by using short-channel MOS transistors operating in the current gain mode. Stacked current mirrors have been utilized as current gain stages to minimize the effects of the channel-length modulation in short-channel MOS transistors. Open-circuit gain of 60 to 70 dB, a unity-gain bandwidth of 70 to 100 MHz, and slew-rate of 200 V//spl mu/s were demonstrated at a DC power dissipation of 1-2 mW.