ZGP323：Z8GP 8位微控制器

ZiLOG公司推出新型改善了成本和处理能力的Z8 GP8位微控制器ZGP323。ZGP323系列基于Z8 CISC架构．包括有受欢迎的存储器容量，各种引脚数的封装和较好的处理能力．适合各种范围的应用。     

CS7106GP在数字直流电压表中的应用

本文主要介绍了CS7106GP的性能，特点和功能，及其在数字直流电压表中的应用。     

基于PCI接口的GPS接收卡的设计

首先介绍了PCI局部总线的信号定义、协议及读写时序，然后给出PCI GPS接收卡的实现方案，并介绍了PCI9025接口芯片、MAX2740射频前端及GP2021十二通道相关器性能特点及技术指标。     

一种基于C674X的GPS接收机硬件方案研究

笔者介绍了以Zarlink公司的GP2015、GP2021芯片组为核心架构,以C6747为相关计算处理器的GPS硬件电路设计,充分考虑了低功耗、高性能及小封装的弹载环境要求;以常用信号捕获算法为基础,给出了GPS定位软件的核心流程框图;最后在完成硬件设计和快捕算法的基础上,进行了导航电文译码检测。     

基于单片机的USB便携多道系统

系统采用MOTOROLA 8位单片机MC68HC908GP32作为中心控制系统,应用其内置8路8位A/D模块实现对多道系统从粒子探测器得到的脉冲电信号进行转换,并通过USB在计算机上以能谱形式显示出来.     

ZiLOG扩展高端马达控制和万能红外遥控市场

一直专注于8位MCU产品的ZiLoG公司在过去的一年内稍微调整了其市场策略。基于面向特定应用市场的专用产品（ASSP）策略，今年年初，ZiLOG宣布进军32位ARM9MCU市场，产品锁定金融POS和安全市场的应用。近日，针对公司8位MCu产品客户对更大容量闪存、更强处理性能的要求，ZiLOG佘司推出了第一款16位MCU产品ZNEO。     

EDN China微控制器在线专题 MCU Online Special

32位处理器以其不可阻挡的性能优势席卷了手持式设备市场，但在更广阔的嵌入式市场还没有太大作为，原因之一是这个市场的用户需求变化得并不象消费类市场那样快。随着以基于Cortex-M3的STM32为代表的32位处理器面世．32位MCU在性能、成本、功耗，已经可以与传统的8位、16位MCU一决高下，尤其是能够采用通用的工具链，重用大量的已有资源。在这种情况下，如何应对市场需求的变化，快速地进行开发、验证和测试。     

ZiLOG推32位MCU战略主攻安防及税控市场

当业界还在为到底是8位、16位、还是32位MCU更有发展潜力而争论不休时，那些专注于MCU技术的厂商们仍然埋头于新产品新技术的创新和新市场策略的谋划。去年10月，8位单片机出货量全球第一的Microchip宣布进入16位市场，因为它看到16位MCU市场增长潜力巨大。而近日，以做MCU起家、主推8位机的ZiLOG推出其32位MCU战略，但它声称主攻安全及销售点（POS）市场。     

全球半导体器件市场新态

MCU厂商往往会越过16位MCU直接开发32位MCU，而8位MCU量产又在不断增大，16位CMU在价格上敌不过8位MCU，性能上又容易被32位MCU所替代，再加上32位MCU价格迅速下跌，使16位MCU处于十分尴尬的局面。美国微芯和赛普拉斯把MCU的重点放在8位MCU上，微芯于2004年4月销售出第30亿块8位MCU，1999年销售出第10亿块8位MCU，2002年春销售出第20亿块8位MCU，表明8位MCU深受市场的欢迎。     

嵌入式处理器:基于多核架构引领32位之争

嵌入式系统以各种类型的嵌入式处理器为核心，而随着技术的发展，对于嵌入式处理器的性能及功耗的要求愈加严苛。目前，嵌入式处理器分为8位、16位、32位及64位等，8位微处理器／MCU市场已逐步趋向稳定，32位微处理器／MCU则代表着嵌入式技术的发展方向，据调查显示，在亚洲各个地区，32位嵌入式处理器的应用明显领先于其它架构。     

高动态接收机的关键问题研究

为检测高动态GPS(Global Positioning System)信号,需要设计码环及载波环的捕获与跟踪数字系统.在高动态下,在GPS信号的码跟踪和载波捕获与跟踪问题中最关键的是要解决在高加速度下的载波跟踪问题.主要讨论了在高动态下,结合GEC公司的十二通道相关器GP2021,载波跟踪环路的特性并在此基础上提出了一个新的方法来改善载波跟踪环路的性能.     

Experimental evaluation of combined postdetection diversity andconcatenated channel coding

The combined effects of postdetection diversity reception and concatenated channel coding are experimentally evaluated for π/4-shift QDPSK signal transmission over a Rayleigh fading channel. Two-branch postdetection diversity reception using maximal ratio combining (MRC) and selection combining (SC) are considered. The concatenated channel coding uses the Reed-Solomon (15,k) code of GP(2 ⁴) as the outer code and the BCH (7,4) code as the inner code (k=9,11,13). Measured bit error rate (BER) performance results are presented under cochannel interference (CCI) and multipath channel delay spread, as well as additive white Gaussian noise (AWGN)     

一个65nm GP CMOS工艺0.06mm2 1.0V 2.5mW 10bit 250MS/s 电流舵数模转换器

A10 bit 250 MS/s current-steering digital-to-analog converter is presented. Only standard Vv core de- vices are available for the sake of simplicity and low cost. In order to meet the INL performance, a Monte Carlo model is built to analyze the impact of mismatch on integral nonlinearity （INL） yield with both end-point line and best-fit line. A formula is derived for the relationship oflNL and output impedance. The relation of dynamic range and output impedance is also discussed. The double eentroid layout is adopted for the current source array in order to mitigate the effect of electrical, process, and temperature gradient. An adapted current mirror is used to over- come the gate leakage of the current source array, which cannot be ignored in the 65 nm GP CMOS process. The digital-to-analog converter occupies 0.06 mm2, and consumes 2.5 mW from a single 1.0 V supply at 250 MS/s.     

基于RISC技术的实现单字节乘法的MCU设计

基于RISC技术实现单字节乘法的微控制器设计主要包括：RISC指令集的选取、取指单元、译码单元、执行单元的设计.该微控制器包含8个模块：8位指令存储器、12位程序计数器、12位地址选择器、可进行16位加法的算术运算器、16位累加器、16选8的数据选择器、8位数据控制器以及状态机.为了进行测试,又增加了3个外围模块：RAM,ROM和addr_decode.设计使用可综合的Verilog 语言描述,Modelsim 5.7 PE软件仿真.     

Partitioned-charge-based modeling of bipolar transistors for non-quasi-static circuit simulation

The concept of partitioned-charge-based (PC) modeling of bipolar transistors is developed and demonstrated, and shown to be fundamentally superior to conventional quasi-static charge-control modeling, the basis of the common (capacitance-based) Gummel-Poon (GP) equivalent circuit. SPICE transient simulations with PC and GP models are contrasted to show a first-order accounting for non-quasi-static (NQS) delay in the PC model which is not accounted for in the GP model. Additional model contrasts in the small-signal domain, compared with exact ac solutions, confirm the superiority of the PC model, the characterization of which is in fact no more tedious than that of the GP model.     

Bit Error Probability and Bit Outage Rate in Chaos Communication

This paper investigates the notion of the probability of bit error (PBE) and its distribution in chaos-based communication systems; these are seen as being the fundamental quantities to both the well-known bit error rate (BER) and the new concept in chaos communications of bit outage rate (BOR). The form of the distribution illustrates the degree to which bit error rate is a stable representation of performance. Bit outage rate is another measure of performance which gives practically helpful information about bit error. For a simple coherent chaos-shift-keying system the distribution of bit error probability is derived exactly, and theoretically exact formulas for the bit outage rate and bit error rate are presented. Two specific cases are developed to obtain useful qualitative and quantitative information. The cases concern independent Gaussian spreading, as a lower benchmark and logistic map spreading, as typical of effective chaotic spreading. Comparisons are obtained between these spreading distributions and between different extents of their spreading, calibrated against per bit signal to noise ratio. A general conclusion is that bit outage and bit error rates are complementary measures of performance.     

数字音频中的1 bit技术

文中探讨数字音频中的1bit技术，分析了采用1bit信号流的录音和放音方法。介绍了1bit A/D和D/A转换，超级音频光盘（SACD）和1bit数字扩大机、指出了1bit技术应用于数字扬声器的可能性和1bit技术在数字音频中的应用前景。     

Quantization of Multiple Sources Using Nonnegative Integer Bit Allocation

Asymptotically optimal real-valued bit allocation among a set of quantizers for a finite collection of sources was derived in 1963 by Huang and Schultheiss, and an algorithm for obtaining an optimal nonnegative integer-valued bit allocation was given by Fox in 1966. We prove that, for a given bit budget, the set of optimal nonnegative integer-valued bit allocations is equal to the set of nonnegative integer-valued bit allocation vectors which minimize the Euclidean distance to the optimal real-valued bit-allocation vector of Huang and Schultheiss. We also give an algorithm for finding optimal nonnegative integer-valued bit allocations. The algorithm has lower computational complexity than Fox's algorithm, as the bit budget grows. Finally, we compare the performance of the Huang-Schultheiss solution to that of an optimal integer-valued bit allocation. Specifically, we derive upper and lower bounds on the deviation of the mean-squared error (MSE) using optimal integer-valued bit allocation from the MSE using optimal real-valued bit allocation. It is shown that, for asymptotically large transmission rates, optimal integer-valued bit allocations do not necessarily achieve the same performance as that predicted by Huang-Schultheiss for optimal real-valued bit allocations     

基于FM0记忆辅助特性的RFID标签碰撞检测

为实现两个射频识别(RFID)碰撞标签信息的检测和分离，提出一种利用Gen2标准中FM0标签编码固有记忆特性的检测方法。通过对FM0比特编码特点和碰撞标签信息的无记忆检测分析，得到基于单个比特持续时间的无记忆检测方法的条件错误概率和单个标签信息检测的误码率；然后利用单个FM0比特编码需要前一比特的“记忆”特性，得到对应于前一比特的一对测量值和对应于下一比特的一对测量值，进而得到碰撞标签信息的1比特记忆辅助检测时的条件错误概率和误码率性能；并对在帧Aloha媒质接入方案中采用提出的检测方法时的N个标签群的总延迟减少性能进行了分析。仿真实验结果表明，提出的1比特记忆辅助检测方法，相比于无记忆检测具有更好的误码率性能，且能减少标签群接入时的总延迟。