0.13μm铜互连工艺鼓包状缺陷问题的解决

传统集成电路制造工艺主要采用铝作为金属互连材料,但是随着晶体管尺寸越来越小,在0.13μm及以上制程中,一般采用铜大马士革互连工艺来提高器件的可靠性。铜互连工艺中需要用氮化硅作为穿孔图形蚀刻的阻挡层,由于氮化硅材质具有很强的应力,再加上制程中的热反应和蚀刻效应就会造成氮化硅层从界面掀起从而形成一种鼓包状缺陷(bubble defect)。文章通过调整并控制铜金属连线层间氧化电介质层的蚀刻速率,改变有机介质层(BARC)的沉积方法,以及改进产品的电路设计的检验规则,从而解决鼓包状缺陷的产生,降低产品芯片的报废率,提高产品的良率。     

铜互连氮化硅薄膜沉积技术中电压衰减的研究

根据0.13 μm以下的深亚微米超大规模集成电路中先进的后道铜互连技术对于氮化硅薄膜沉积的具体要求,文章在大马士革工艺的基础上分析了可能导致铜互连失效的原因.进而在应用材料公司的PRODUCER(一种薄膜沉积设备)机台上,通过包括对氨等离子体预处理和氮化硅预沉积的这两步骤作实验研究.利用田口分析判断的实验方法,找到主要...     

真空退火对低频PECVD氮化硅薄膜性能的影响

研究了真空退火温度对不同流量比工艺参数下PECVD氮化硅薄膜性能的影响,测试了退火后氮化硅薄膜厚度、折射率以及在氢氟酸中的腐蚀速率。结果表明,退火后氮化硅薄膜厚度及折射率变化与薄膜沉积工艺条件有关,而薄膜在氢氟酸中的腐蚀速率在退火后大大降低。结合退火前后氮化硅薄膜的红外透射谱对以上测试结果进行了讨论。     

晶体硅太阳电池减反射膜的研究

在太阳电池表面形成一层减反射薄膜是提高太阳电池的光电转换效率比较可行且降低成本的方法。应用PECVD（等离子体增强化学气相沉积）系统,采用SiH4和NH3气源以制备氮化硅薄膜。研究探索了PECVD生长氮化硅薄膜的基本物化性质以及在沉积过程中反应压强、反应温度、硅烷氨气流量比和微波功率对薄膜性质的影响。通过大量实验,分析了氮化硅薄膜的相对最佳沉积参数,并得出制作减反射膜的优化工艺。     

变温LPCVD沉积氮化硅薄膜的均匀性优化

以低压化学气相沉积(LPCVD)热壁立式炉为实验平台,由二氯硅烷和氨通过LPCVD工艺合成氮化硅薄膜,利用降温成膜提高氮化硅薄膜的膜厚均匀度。基于气体碰撞理论建立了氮化硅薄膜沉积速率与反应气体浓度的关系式。分析比较了LPCVD炉内不同升温速率沉积氮化硅薄膜的表面性能。发现在变温沉积阶段,选择合适的降温速率是实现薄膜沉积过程中预设温度变化的关键。在保证各温度区平均膜厚和晶圆片之间膜厚均匀度基本不变的前提下,通过实验找到沉积阶段的最佳变温速率,将晶圆片内(WIW)均匀度优化到1%以下,比恒温沉积薄膜的均匀度提高了约70%。这将有助于设备工艺能力的提升,更好地适应IC芯片工艺关键尺寸的缩小趋势。     

LPCVD制备氮化硅薄膜工艺

氮化硅（摘要）薄膜具有许多优良特性,在半导体、微电子和MEMS领域应用广泛。本文简要介绍了利用CVD方法制备摘要薄膜以及Si3N4薄膜的特性,详细介绍了低压化学气相淀积（Low Pressure Chemical Vapor Deposition）LPCVD制备氮化硅的工艺。工艺制备中通过工艺参数的调整使批量生产的淀积膜的均匀性达到技术要求。     

PECVD法氮化硅薄膜制备工艺的研究

采用等离子体增强化学气相沉积法（PECVD）在单晶硅衬底上制备了氮化硅薄膜,分别使用膜厚仪、椭圆偏振仪等手段对薄膜的厚度、折射率等参数进行了表征。研究了硅烷氨气流量比、极板间距等工艺参数对氮化硅薄膜性能的影响,发现当硅烷氨气流量比增加时,薄膜厚度和折射率均随之增加,并发现退火工艺可以有效降低氮化硅薄膜的氢氟酸腐蚀速率。     

沉积功率和气压对低频氮化硅薄膜应力的影响

利用等离子体增强化学气相沉积(PECVD)工艺,在不同射频功率,不同反应气压条件下制备了氮化硅薄膜。研究了低频工艺中氮化硅薄膜的沉积速率、应力以及厚度均匀性与其二者的关系。结果表明,射频功率的改变直接影响到离子对衬底的轰击效应,而反应气压的改变影响气体分子的平均自由程。离子轰击效应和分子平均自由程对氮化硅薄膜的生长过程产生影响,从而影响沉积速率、应力以及厚度均匀性等基本性质。     

CdS纳米薄膜的水浴法制备与表征

CdS是一种直接能隙半导体，其带隙约为2．42eV，是一种良好的太阳能电池窗口层材料和过渡层材料。化学水浴法沉积CdS薄膜具有工艺简单，成本低廉，成膜均匀、致密以及可大面积生产等优点。本文通过对化学水浴法沉积CdS薄膜的研究，阐述了CdS膜的生成和生长过程及其机理，并不断优化此方法中的各种工艺参数，得到了适合做铜铟镓硒薄膜太阳能电池过渡层的CdS薄膜，并对该薄膜的形貌、结构和性能进行了分析。     

PECVD法氮化硅薄膜生长工艺的研究

采用等离子体增强化学气相沉积法(PECVD),在单晶硅衬底(100)上成功制备了不同生长工艺条件下的氮化硅薄膜。分别采用XP-2台阶仪、椭圆偏振仪等手段测试了薄膜的厚度、折射率、生长速率等参数。并采用原子力显微镜(AFM)研究了薄膜的表面形貌。结果表明,温度和射频功率是影响薄膜生长速率的主要因素,生长速率变化幅度可以达到230nm/min甚至更高。对于薄膜折射率和成分影响最大的是NH3流量,折射率变化范围可以达到2.7～1.86。分析得出受工艺参数调控的薄膜生长速率对薄膜的性质有重要影响。     

Modeling the growth of PECVD silicon nitride films for solar cellapplications using neural networks

Silicon nitride films grown by plasma-enhanced chemical vapor deposition (PECVD) are useful for a variety of applications, including anti-reflection coatings in solar cells, passivation layers, dielectric layers in metal/insulator structures, and diffusion masks, PECVD nitride films are known to contain hydrogen, and defect passivation by hydrogenation enhances efficiency in polycrystalline silicon solar cells. PECVD systems are controlled by many operating variables, including RF power, pressure, gas flow rate, reactant composition, and substrate temperature. The wide variety of processing conditions, as well as the complex nature of particle dynamics within a plasma, makes tailoring Si₃N₄ film properties very challenging, since it is difficult to determine the exact relationship between desired film properties and controllable deposition conditions. In this study, silicon nitride PECVD modeling using neural networks has been investigated. The deposition of Si₃N₄ was characterized via a central composite experimental design, and data from this experiment was used to train optimized feed-forward neural networks using the back-propagation algorithm. From these neural process models, the effect of deposition conditions on film properties has been studied. It was found that the process parameters critical to increasing hydrogenation and therefore enhancing carrier lifetime in polysilicon solar cells are temperature, silane, and ammonia flow rate. The deposition experiments were carried out in a Plasma Therm 700 series PECVD system     

Optimization of saturation current density of PECVD SiN coated phosphorus diffused emitters using neural network modeling

Emitter surface passivation by low temperature plasma enhanced chemical vapor deposition (PECVD) silicon nitride is investigated and optimized in this paper. We have found that the saturation current density of a 90±10 μ/sq phosphorus diffused emitter with N_s ≈3 x 10¹⁹ and X_j ≈0.3 μm can be lowered by a factor of eight by appropriate PECVD silicon nitride deposition and photoassisted anneal. PECVD silicon nitride deposition alone reduces the emitter saturation density (J_oe) by about a factor of two to three, and a subsequent photoanneal at temperatures ≥350°C reduces J_oe by another factor of three. In spite of the larger flat band shift for direct PECVD silicon nitride coating, the silicon nitride induced surface passivation is found to be about a factor of two inferior to the thermal oxide plus PECVD silicon nitride passivation due to higher interface state density at the SiN/SiO₂ interface compared to SiO₂/Si interface. A combination of statistical experimental design and neural network modeling is used to show quantitatively that lower radio frequency power, higher substrate temperature, and higher reactor pressure during the PECVD deposition can reduce the J_oe of the silicon nitride coated emitter.     

Bulk and surface passivation of silicon solar cells accomplished by silicon nitride deposited on industrial scale by microwave PECVD

Bulk and surface passivation by silicon nitride has become an indispensable element in industrial production of multicrystalline silicon (mc‐Si) solar cells. Microwave PECVD is a very effective method for high‐throughput deposition of silicon nitride layers with the required properties for bulk and surface passivation. In this paper an analysis is presented of the relation between deposition parameters of microwave PECVD and material properties of silicon nitride. By tuning the process conditions (substrate temperature, gas flows, working pressure) we have been able to fabricate silicon nitride layers which fulfill almost ideally the four major requirements for mc‐Si solar cells: (1) good anti‐reflection coating (refractive index tunable between 2·0 and 2·3); (2) good surface passivation on p‐type FZ wafers (S_eff<30 cm/s); (3) good bulk passivation (improvement of IQE at 1000 nm by 30% after short thermal anneal); (4) long‐term stability (no observable degradation after several years of exposure to sunlight). By implementing this silicon nitride deposition in an inline production process of mc‐Si solar cells we have been able to produce cells with an efficiency of 16·5%. Finally, we established that the continuous deposition process could be maintained for at least 20 h without interruption for maintenance. On this timescale we did not observe any significant changes in layer properties or cell properties. This shows the robustness of microwave PECVD for industrial production. Copyright © 2005 John Wiley & Sons, Ltd.     

大马士革工艺中等离子体损伤的天线扩散效应

等离子体技术的广泛应用给工艺可靠性带来了挑战,等离子体损伤的评估成为工艺可靠性评估的重要内容之一。针对大马士革工艺中的等离子体损伤问题,提出了天线扩散效应,确定了相应工艺的天线扩散系数,提高了工艺可靠性评估的准确性。根据不同介质层沉积对器件的影响,确定了等离子体增强化学气相沉积(PECVD)是大马士革工艺中易造成等离子体损伤的薄弱环节之一。实验结果表明,同种工艺满足相同的天线扩散效应,此时工艺参数的改变不会影响天线扩散系数。对带有不同天线结构的PMOS器件进行可靠性分析,得知与密齿状天线相比,疏齿状天线对器件的损伤更严重,确定了结构面积和间距是影响PECVD工艺可靠性水平的关键参数。     

The application of polyimide/silicon nitride dual passivation to AlxGa1−xN/GaN high electron mobility transistors

PECVD silicon nitride passivation is quite frequently done at the end of AlGaN/GaN HEMT fabrication before substrate back-side lapping. However, the PECVD silicon nitride process is likely to produce pinholes in the passivation film. A very thick PECVD silicon nitride film may produce mechanical stress on the underlying device. Polyimide passivation has also been known to be effective for AlGaN/GaN HEMT and it can also serve as a stress buffer. However, polyimide can take up water while PECVD silicon nitride is a good diffusion barrier for water, etc. Thus it is expected that a dual PECVD silicon nitride/polyimide passivation will be a better choice than just a single layer of PECVD silicon nitride or polyimide. In this paper, we will demonstrate the application of a dual PECVD silicon nitride/polyimide passivation to AlGaN/GaN HEMT process.     

Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O₂/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.     

New applications of low temperature PECVD silicon nitride films for microelectronic device fabrication

Silicon nitride has been widely used in microelectronic device fabrication processes for encapsulation, surface passivation and isolation. In this paper we report new applications of plasma-enhanced chemical vapor deposition (PECVD) silicon nitride films that can be deposited at a temperature lower than the soft bake temperature of normal photoresists. Lift-off of the silicon nitride film was carried out using standard positive photoresist. GaAs MESFETs and InP MISFETs with self-aligned gates were successfully fabricated using this lift-off process of low temperature PECVD silicon nitride.     

High efficiency polycrystalline silicon solar cells using lowtemperature PECVD process

Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (~10 nm) of PECVD SiO₂ is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si₃N₄) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si₃N₄. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl₃ gettering, hydrogen rf plasma/PECVD Si₃N₄ and PECVD SiO₂ passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si₃N₄ layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si₃N₄ layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500°C. Low temperature (⩽400°C) annealing of the PECVD Si₃N ₄ provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells     

Wafer bonding for III–V on insulator structures

The InP and GaAs wafers were bonded to GaAs substrates using a siliconnitride intermediate layer. Key process parameters include the silicon-nitride surface roughness and density as determined by atomic-force microscopy and x-ray reflectivity. We demonstrate that silicon nitride can be bonded without any chemical-mechanical polishing step. Silicon-nitride films produced by plasma-enhanced chemical-vapor deposition (PECVD) and deposition by sputtering were compared for bonding compatibility. Smooth silicon-nitride layers (root-mean-square roughness <0.7 nm) were found to produce large areas of bonded material and an oxygen-plasma treatment (200 mtorr, 200 W, 60 s) produced strong nitride/nitride bonding. The strain in the InP layer after transfer to the GaAs substrate was determined using x-ray reciprocal-space mapping (RSM). The crystalline quality of the InP layer was examined with high-resolution x-ray scattering.     

深亚微米集成电路工艺中铜金属互联技术

本文介绍了铜互联技术在深亚微米半导体工艺中的应用,重点介绍了铜金属互联技术中的关键工艺,包括在器件中采用铜金属互联线以降低互联延迟,大马士革（Damascene）结构微细加工工艺,物理汽相淀积（PVD）技术制备铜扩散阻挡层（Barrier）和铜子晶层（Cu-seed）,铜金属层化学电镀技术（Electroplating）,对铜金属互联工艺集成方面的要点也作了一些探讨。