基于工艺参数扰动的随机互连线时延分析

考虑工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的互连线随机模型.通过改进的去耦算法对随机互连线元进行去耦,结合随机伽辽金方法(SGM)和多项式混沌展开(PCE)进行互连分析,进而利用复逼近及二分法给出工艺参数扰动下互连时延的有限维表达式.仿真实验结果不仅与SPICE仿真吻合得较好,相较于SPICE蒙特卡洛仿真还具有更高的计算效率.     

工艺随机扰动下非均匀RLC互连线串扰的谱域方法分析

 考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率.     

工艺变化下互连线建模与ABCD参数仿真

考虑互连线工艺变化的空间相关性,采用数值仿真及拟合方法,得到电气分布参数的近似表达式,建立了互连线分布参数随机模型;推导出互连线ABCD参数满足的随机微分方程组,并提出基于蒙特卡洛法的ABCD参数统计分析方法;最后,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出最差情况估计.实验结果表明,提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估.     

随机工艺变化下互连线ABCD参数建模与仿真

集成电路的不断发展使得互连线的随机工艺变化问题已经成为影响集成电路设计与制造的重要因素。基于电报方程建立了工艺变化下互连线的分布参数随机模型,推导出互连线ABCD参数满足的随机微分方程组,并提出了基于蒙特卡洛法的互连线ABCD参数统计分析方法,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出了最差情况估计。实验结果表明所提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估。     

FPGA中通用互连结构的设计与优化

介绍了一款基于SRAM技术的FPGA电路的通用互连结构.在对其通用互连线的延时模型进行分析的基础上,提出了一种改进的互连结构.基于CSMC 0.6 μm工艺下的SPICE仿真及流片结果表明,改进后的互连结构性能提高了约10%.     

VLSI随机工艺变化下互连线建模与延迟分析

目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素.考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证.     

相控阵导引头捷联去耦方法及性能分析

相控阵导引头全捷联安装在弹体上,波束指向易受弹体姿态扰动影响,从而影响探测性能。需采取相应的捷联去耦措施,隔离弹体扰动,实现波束在惯性空间的指向稳定。分析了弹载相控阵导引头捷联去耦的特性,给出一种实用的相控阵导引头捷联去耦方法,通过仿真试验对导致相控阵导引头不完全解耦的因素进行了系统分析,得出满足弹载环境去耦系数需求时,对部分雷达参数设计的约束。     

不确定随机变时滞神经网络的全局渐进稳定性

采用It(o)'s微分公式和不等式分析技巧,研究了一类不确定随机变时滞神经网络的全局渐进稳定性问题.该模型同时考虑了神经网络模型的两种扰动因素,即随机扰动与不确定性扰动.不确定性参数是时变且范数有界的.通过构造适当的Lyapunov泛函,以线性矩阵不等式形式给出了平衡点在均方根意义下的全局渐进稳定性判据,能够利用LMI工具箱很容易地进行检验.此外,仿真示例证明了结论的有效性.     

工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

65 nm的互连线工艺灵敏度分析

集成工艺尺寸的不断缩小使得工艺偏离效应(process variation)成为实现集成电路高成品率设计的关键.本文通过互连线工艺灵敏度分析来探讨工艺偏离效应问题.首先利用TCAD软件仿真单变量试验样本,对仿真样本数据统计3-σ值,定性分析灵敏度关系.然后用最小二乘法拟合曲线,定量分析65nm的互连线工艺灵敏度.分析结果表明互连线寄生参数随互连线宽度变化最为显著.     

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.     

Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints

Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect.     

高速互连线CAD技术研究

采用边界积分方程结合矩量法计算高速互连线电磁参数,讨论了版图关键互连线提取技术和互连的ＳＰＩＣＥ模型建立技术,并用ＳＰＩＣＥ简要分析了互连线效应。     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

Delay analysis of buffer inserted sub-threshold interconnects

In this paper, an analysis of interconnect delay minimization by CMOS buffer insertion in sub-threshold regime is presented. Analytical expressions are developed to calculate the total delay and optimum number of buffers required for delay minimization in sub-threshold interconnects. Considering delay minimization by buffer insertion, the effects of voltage-scaling on the delay and optimum number of buffers have been analyzed. It is demonstrated that voltage scaling in sub-threshold regime reduces the number of buffers required to attain the minimum delay. This is one more advantage of voltage-scaling in addition to the usual reduction in power dissipation, in the sense that lesser silicon area is consumed. For a wide variety of typical interconnect loads, analytically obtained results are in good agreement with SPICE extracted results for most of the cases more than 90 %. Finally, the variability analysis of sub-threshold interconnects is investigated using Monte Carlo analysis.     

一种新的集成电路互连线串扰模型和估计公式

建立了一个考虑分布电阻,分布电容的互连线混П模型,在这个模型的基础上,分析了终端在最坏条件下的串扰响应,并推导了三阶S域系数的精确表达式,最终,获得了一个新的互连线串扰响应的估计公式,通过与SPICE模拟的结果相比较,该文的模拟结果非常接近实际电路的串扰响应,与相关文献所发表的结果相比较,该模型更符合实际情况,结果也更精确。