VA液晶显示器光程差测量方法分析

垂直排列Vertical Array简称VA,VA液晶显示器盒内液晶分子的排列方式是垂直排列,因此采用现有常用的光程差测试设备如CG-200,无法测量出VA液晶显示器的光程差。文章研究利用VA液晶显示器的显示机理,通过测试比较不同光程差对应的高压光电曲线,总结出测量VA液晶显示器光程差的简单方法。     

电控平行排列液晶光栅的光衍射特性研究

对电控平行液晶光栅的理论进行了分析,并配以结构原理图。通过对平行排列及90°扭曲排列液晶指向矢的计算,得出液晶盒中相应的折射率、相位差与电压之间的关系图,两者经比较证明平行排列更具适用性,并在实验中观测到了平行排列液晶光栅衍射特性与电压的关系。     

光控取向弱锚定表面的液晶分子排列

研究了光敏聚酰亚胺ＰＩ（ＢＴＤＡ－ＴＭＭＤＡ）用于液晶取向时的弱锚定边界特性。实验测得了两基板皆为摩擦取向层扭曲向列液晶显示器件（ＤＲ－ＴＮ－ＬＣＤ）及两基板皆为光控取向层的扭曲向列液晶显示器件（ＤＬＰＰ－ＴＮ－ＬＣＤ）的电光特性和时间响应特性曲线。研究了液晶排列的稳定性,讨论了液晶分子在光控取向弱锚定表面上的排列机理。     

液晶盒的电容特性

液晶盒外加一定的电压,会改变液晶分子的取向排列,这样液晶层的有效介电常数也会随之发生改变。如果把液晶盒看作一个电容器,其电容也会有所改变。本论文理论研究强锚泊混合排列向列相液晶盒的电容特性,基于液晶弹性理论和变分原理,理论推导液晶盒系统的平衡态方程及电容的解析表达式,通过Matlab软件数值模拟了此液晶盒的电容-电压曲线和指向矢分布曲线,并对其电容特性进行了分析。     

电场对铁电液晶分子排列的影响

本文通过在铁电液晶相变过程中施加交变电场的方法，研究了电场对铁电液晶分子排列的作用。实验表明在液晶相变点附近施加低频交变电场，能够使铁电液晶分子形成均匀排列，从而提高了铁电液晶器件的记忆效应与对比度，最后我们给出了合理的理论解释。     

改进的极向锚定强度测量方法

介绍一种测量液晶表面极向锚定强度的方法,通过同步测量线性偏振光经过混合排列的楔形液晶盒的相位及外加电压值,经过数值处理,得到表面极向锚定强度。使用混合排列液晶盒,简化了计算及测量步骤;使用楔形盒并用不同点的厚度差值代替厚度值计算,减小了由于厚度测量误差引起的干扰,提高了测量精度。     

新型多畴扭曲向列相液晶显示器

提出在像素电极下方放置凸起物,获得具有宽视角特性的多畴扭曲向列相液晶显示器。该模式比传统的多畴TN模式摩擦过程少,工艺过程简单。在这种液晶显示器中,初始状态(未加电)时,分子排列结构和普通单畴TN模式相同,在加电压状态时,由于凸起物的存在,液晶分子沿着4个不同的方向排列形成多畴区域。文中运用专业液晶模拟软件模拟,对该液晶显示器的电光特性进行研究,结果表明,该液晶显示器具有宽视角、色散小及色彩还原性较好的特性。     

垂直定向液晶光阀及光电特性的研究

系统地讨论了排列相畸变模式液晶光阀结构，原理和制作，结合实际测试对其等效电路和电学匹配进行了分析，详细讨论了它的光电特性及相互关系，实测的液晶垂直排列方式工作的液晶光阀性能指标为，分辨率大于５０ｌｐ／ｍｍ，白光输入灵敏度为６．７７μＷ／ｃｍ＾２，响应时间为２００ｍｓ／３００ｍｓ，白光输出对比度为２００：１。     

用强化环硅氧烷使液晶取向

首次研究了用带平面和立体结构以及分子中张紧键的环硅氧烷来获得使液晶取向的膜。研究了取向膜的制备条件及其特性。确定了获得指定液晶排列的最佳参数。     

无序的混合排列型ECB—LCD的研究

为了改善常规的ＥＣＢ的显示品质，采用不摩擦技术制备无序的混合排列型ＥＣＢ液晶盒，分析了它的电光特性和视角特性。无序的混合排列型ＥＣＢ液晶盒是多畴的结构，并具有很多向错，但人的肉眼却识别不出。无序的混合排列型ＥＣＢ器件具有三色峰值电压分离较好、工作电压低、视角在整个平面内具有方位角对称性的特点。     

一种改进的C-V方法对向列相液晶弹性常数k11、k33测量的理论研究

提出了一种更为准确的测量向列相液晶展曲、弯曲弹性常数的C-V方法。以正性液晶材料为例,当沿面排列的液晶分子预倾角不为零时,阈值电压值不易确定,k11的确定必定存在误差,而以前报道并未考虑到此问题。文章针对此问题给出了在强锚定条件下,预倾角不为零时C-V的关系式,并提出了通过曲线拟合来同时确定弹性常数k11、k33的方法。此方法对弹性常数的测量更为准确,液晶盒的制作要求降低,且测试简单、易操作。     

深亚微米MOSFET阈值电压模型

文章在分析短沟道效应和漏致势垒降低(DIBL)效应的基础上,通过引入耦合两效应的 相关因子,建立了高k栅介质MOSFET阈值电压的器件物理模型。模拟分析了各种因素对阈值电 压漂移的影响,获得了最佳的k值范围。     

逆F类放大器漏极电压波形研究

为了更清晰地了解逆F类功率放大器通过规整漏极电压和电流波形实现高效率的本质,对其漏极电压波形进行了理论分析和仿真验证。结果表明,在仅考虑二、三次谐波,且当谐波比例k=1/4时,v(θ)波形最平坦,最近似于半正弦波。利用电磁软件仿真设计并制作了一款k=0.271的逆F类功率放大器,经测试在输出功率为36.33 dBm时,功率附加效率达到了71%。     

Bottom-contact organic field-effect transistors based on single-crystalline domains of 6,13-bis(triisopropylsilylethynyl) pentacene prepared by electrostatic spray deposition

Large crystalline domains (a few hundred micrometers in size) of 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS pentacene) were prepared by electrostatic spray deposition (ESD) and used as the active layers of bottom-contact organic field-effect transistors. The TIPS pentacene active layers were directly patterned via a shadow mask in the ESD process. The device, which had a 5-μm-long channel composed of a single-crystalline domain, exhibited a high field-effect mobility of more than 0.1 cm²/V s but resulted in a high threshold voltage of −17 V. The threshold voltage could be lowered to −6.4 V by reducing the thickness of the BC electrodes from 30 to 10 nm; this threshold voltage lowering was probably due to an improvement in the charge injection from the source electrode to the active layer.     

一种P-GaN栅结合混合帽层结构的HEMT器件

为了进一步提升P-GaN栅HEMT器件的阈值电压和击穿电压,提出了一种具有P-GaN栅结合混合掺杂帽层结构的氮化镓高电子迁移率晶体管(HEMT)。新器件利用混合掺杂帽层结构,调节整体极化效应,可以进一步耗尽混合帽层下方沟道区域的二维电子气,提升阈值电压。在反向阻断状态下,混合帽层可以调节栅极右侧电场分布,改善栅边电场集中现象,提高器件的击穿电压。利用Sentaurus TCAD进行仿真,对比普通P-GaN栅增强型器件,结果显示,新型结构器件击穿电压由593 V提升至733 V,增幅达24%,阈值电压由0.509 V提升至1.323 V。     

Low voltage CCD image sensor with optimized reset operation

A charge coupled device (CCD) image sensor operating with 3.0 V-reset has been developed using a charge injection to the gate dielectrics of a MOS structure. A DC bias generating circuit was added to the reset structure, which sets reference voltage and holds the signal charge to be detected. The generated Dc bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2 to 5.5 V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with 492(H)×510(V) pixels adopting this structure showed complete reset operation with the driving voltage of 3.0 V. The image taken with the image sensor utilizing this structure was not saturated to the illumination of 30 lux, that is, showed no image distortion.     

Reduction of threshold voltage for bistable liquid-crystal switching using a priming voltage

A method is described for reducing the threshold field required to achieve high-speed matrix addressing of a bistable nematic liquid-crystal storage display. A short ac priming voltage pulse applied to the device modifies the binding energy for disclinations attached to sites of orientational discontinuity, thereby changing the threshold field for electrical switching between bistable states. The threshold reduction depends on the ac frequency and width of the writing pulse. The physical mechanism underlying this effect is described. Matrix addressing (3:1) with 2-ms pulses has been demonstrated with select voltage levels as low as 2 V0= 70 V and nonselect levels of V0= 35 V.     

A new two-dimensional threshold voltage model for cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs

Based on two-dimensional (2D) Poisson potential solution, a compact, analytical model for threshold voltage in cylindrical, fully-depleted, surrounding-gate (SG) MOSFETs is successfully derived. The minimum surface potential _min,surface is used to develop the threshold voltage model. Besides decreasing the characteristic factor, both the thin silicon body and gate oxide can reduce the threshold voltage roll-off simultaneously. It is also found that the threshold voltage shift is dependent on the scaling factor of λ₁L. The high scaling factor is preferred to alleviate threshold voltage degradation.     

MOSFET's in the 0°K approximation: Static characteristics of MOSFET's in the 0°K approximation

The static electrical characteristics below current saturation of MOSFET's with degenerate source and drain regions are calculated for operation at 0°K. The expression for current takes the same form as at room temperature although the flat-band voltage and the voltage across the depletion region at threshold are altered slightly. Potential hills occur in the channel if the gate does not overlap source and drain or if the oxide thickness is increased in the overlap regions. Although these barriers do not affect operation appreciably at room temperature, at 0°K a finite drain voltage (source-drain threshold voltage) is required to initiate conduction. This threshold voltage is included in the theory and the theory is compared with experimental results on p-channel enhancement mode MOSFET's at 4·2°K using hole mobility in the channel as a matching parameter. The channel hole mobility (assumed constant along the channel) is found to be relatively independent of gate voltage but to increase with increasing (negative) drain voltage. Values ranging between 500 and 1000 cm²/V-sec are deduced for drain voltages ranging from ?1·2 V to ?7 V. This compares to channel hole mobility values of 200–300 cm²/V-sec at room temperature. It is found that the channel width is on the order of 30–50 Å—appreciably less than that at room temperature.     

Quantum size impacts on the threshold voltage in nanocrystalline silicon thin film transistors

Based on the analysis of Poisson equation, an analytical threshold voltage model including quantum size effect of nc-TFTs (nanocrystalline silicon thin film transistor) has been proposed in this paper. The results demonstrate that the proposed simplified expression of threshold voltage agree perfectly with numerical calculation. The threshold voltage in nc-TFTs strongly depends on the size of silicon grain when the size of silicon grain is less than 20 nm. Such a strong dependent relation results from the large changes in the bandgap and dielectric constant due to quantum size effects when the size of silicon grain is in the regime of nano-scale. The theoretical investigation also demonstrates that the grain boundary trap density compared to the active dopant density gives a main contribution to the threshold voltage. This implies that the grain size must be larger than 30 nm in order to avoid threshold voltage variation from different technological processes.