OFDM系统下LDPC码的性能仿真

通过对LDPC码在不同调制方式下译码算法的分析，把高阶调制下的和积译码算法应用于LDPC—OFDM系统，系统中LDPC码采用目前性能最优的PEG随机构造生成，并与Turbo—OFDM系统进行比较，仿真结果表明短码长LDPC码在高码率高信噪比的情况下性能优于Turbo码。     

一种性能优于Turbo码的LDPC规则码

介绍一种LDPC规则码,其性能优于Turbo码且更接近实用香农极限(1.2dB)。对于LDPC码来讲,稀疏校验矩阵的构造是关键的一步,它影响着码字的性能,这里采用对角线法构造近似下三角形的稀疏校验矩阵,根据此法构造出(n,3,6)的矩阵,满足每行非零元素的个数及分布随机性。译码采用置信传播算法,对此提出矢量化的方法,从而缩减迭代译码时间。     

基于串行消息传递机制的QC-LDPC码快速译码算法研究

针对准循环LDPC(QC-LDPC)码基于洪水消息传递机制译码算法的不足,该文提出了一种快速的分组串行译码算法。该算法通过将LDPC码的校验节点(或变量节点)按一定规则划分成若干个子集,在每一轮迭代过程中,依次对各个子集中的校验节点(或变量节点)并行地进行消息更新,提高了译码速度。同时根据分组规则,提出了一种有效的分组方法,并通过分析发现基于循环置换阵的准循环LDPC码非常适合采用这种分组译码算法进行译码。通过对不同消息传递机制下准循环LDPC码译码算法性能的仿真比较,验证了在复杂度不增加的情况下,该译码算法在继承了串行译码算法性能优异和迭代收敛快等优点的同时,极大地提高了准循环LDPC码的译码速度。分析表明,分组串行译码算法译码速度至少为串行译码算法的p倍(p为准循环LDPC码校验矩阵中循环置换阵的行数或列数)。     

删余Turbo乘积码的编译码算法分析

基于现有的Turbo乘积码的编译码方法,提出一种附加删余的Turbo乘积码编译码算法,介绍其编码器的构造方法,阐述了译码算法及实现框图,分析了删余信息对传输帧长的影响,仿真了其误码性能,并与未删余的Turbo乘积码做比较。分析和仿真结果表明,附加删余的Turbo乘积码可满足特定系统传输速率及帧长的需要,在相同的信噪比下,删余Turbo乘积码的误码性能优于未加删余的误码性能。     

空时分组码分块传输系统中的Turbo检测译码

将基于MMSE的Turbo检测译码方案应用于空时分组码分块传输系统。利用信道矩阵的循环特性，Turbo检测算法可以用FFT/IFFT可快速实现，并且矩阵求逆运算量非常低。仿真结果表明，无论是采用Turbo码还是LDPC码，提出的接收机的性能明显优于传统非迭代的接收机，有1∽2dB的增益。     

多层叠加LDPC码编码调制技术

 本文提出了一种多层叠加LDPC码编码调制系统.与传统的基于速率分配的多层编码调制技术相比,多层叠加编码调制系统具有很好的对称性和可扩展性.通过分析比较Turbo码译码算法与LDPC码的译码算法的复杂度,本文指出了多层叠加LDPC码编码调制系统具有译码简单,易于实现的优点.实验结果表明,多层叠加LDPC码编码调制系统可以在不牺牲带宽的同时获得较好的性能.     

IEEE802.16e标准下LDPC码译码性能分析

LDPC码是一种逼近香农极限的线性分组码。对IEEE802.16e标准下LDPC码校验矩阵的构造及硬判决算法、BP算法、Log-BP算法和Min-Sum算法原理进行了简单介绍。基于Matlab仿真对不同码长译码性能及不同方法译码性能进行分析比较,结果显示随着码长的增加LDPC译码性能变好,讨论的几种译码算法中硬判决译码性能较差,Min-Sum译码好于硬判决译码,但稍差于BP译码和Log-BP译码,BP译码和Log-BP译码性能较好且基本一致。     

LDPC短码的编译码研究

这里研究了原模图LDPC码和BP译码算法,首先提出了一种基于PEG算法构造原模图LDPC码的算法,该码字在码率为1/2,码长256比特的情况下,译码性能超过了PEG算法,然后针对LDPC短码不可避免存在四环的特殊性,提出了一种修正四环中变量节点迭代信息的BP译码改进算法,使得具有四环的LDPC短码的译码性能得到较大提升。     

基于Matlab的Turbo码仿真研究

为了使Turbo码仿真更容易,研究并建立了基于Matlab中Simulink通信模块的Turbo码仿真模型.Turbo码编码器采用两个相同的分量编码器通过交织器并行级联而成.Turbo码译码器采用不同的译码算法,这些算法由S函数调用m文件实现.使用所建立的模型进行仿真,结果表明,在信噪比相同的情况下,交织长度越大、迭代次数越多、译码算法越优,Turbo码性能越好.设计实际系统时,应综合考虑各因素.     

一种短延时Turbo编码调制系统的设计

本文设计了一种比传统体制减少了一半延时的Turbo编码调制系统,介绍了交织器的相关限制.提出了一种在译码过程中对信道值的估计方法,使得外信息的计算更加趋于精确,从而提高了译码性能.这种迭代译码算法是标准格码调制译码算法的一种自然推广,同时也类似于二元Turbo码在BPSK调制下的逐比特译码算法.采用吞吐率为2bits/s/Hz的8PSK调制,比特错误率为10^-5所需的信噪比与Shannon限相距不到0.4dB.     

A Flexible LDPC/Turbo Decoder Architecture

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most powerful error correcting codes that are widely used in modern communication systems. In a multi-mode baseband receiver, both LDPC and Turbo decoders may be required. However, the different decoding approaches for LDPC and Turbo codes usually lead to different hardware architectures. In this paper we propose a unified message passing algorithm for LDPC and Turbo codes and introduce a flexible soft-input soft-output (SISO) module to handle LDPC/Turbo decoding. We employ the trellis-based maximum a posteriori (MAP) algorithm as a bridge between LDPC and Turbo codes decoding. We view the LDPC code as a concatenation of n super-codes where each super-code has a simpler trellis structure so that the MAP algorithm can be easily applied to it. We propose a flexible functional unit (FFU) for MAP processing of LDPC and Turbo codes with a low hardware overhead (about 15% area and timing overhead). Based on the FFU, we propose an area-efficient flexible SISO decoder architecture to support LDPC/Turbo codes decoding. Multiple such SISO modules can be embedded into a parallel decoder for higher decoding throughput. As a case study, a flexible LDPC/Turbo decoder has been synthesized on a TSMC 90 nm CMOS technology with a core area of 3.2 mm². The decoder can support IEEE 802.16e LDPC codes, IEEE 802.11n LDPC codes, and 3GPP LTE Turbo codes. Running at 500 MHz clock frequency, the decoder can sustain up to 600 Mbps LDPC decoding or 450 Mbps Turbo decoding.     

非规则LDPC码在RICE信道中的性能分析

本文对非规则LDPC码在RICE信道的性能进行了分析和仿真,修正了BP译码算法,证明了RICE信道满足对称性,给出了RICE信道译码稳定性条件,推导出了RICE信道的Shannon容量限,采用VC编程对码长N=49512和3072进行了仿真,同时与同码长的Turbo码进行了比较;仿真结果表明LDPC码在码长N＝49512、码率R＝1/3时,与Shannon限相差1dB以内、在低信噪比时其性能优于Turbo码,以及LDPC码本身有很好的交织特性和抗衰落的能力;这进一步表明了LDPC码在包括RICE信道在内的各种信道中的性能都是非常优良的.     

Iterative decoding for partial response (PR), equalized,magneto-optical (MO) data storage channels

Turbo codes and low-density parity check (LDPC) codes with iterative decoding have received significant research attention because of their remarkable near-capacity performance for additive white Gaussian noise (AWGN) channels. Previously, turbo code and LDPC code variants are being investigated as potential candidates for high-density magnetic recording channels suffering from low signal-to-noise ratios (SNR). We address the application of turbo codes and LDPC codes to magneto-optical (MO) recording channels. Our results focus on a variety of practical MO storage channel aspects, including storage density, partial response targets, the type of precoder used, and mark edge jitter. Instead of focusing just on bit error rates (BER), we also study the block error statistics. Our results for MO storage channels indicate that turbo codes of rate 16/17 can achieve coding gains of 3-5 dB over partial response maximum likelihood (PRML) methods for a 10^-4 target BER. Simulations also show that the performance of LDPC codes for MO channels is comparable to that of turbo codes, while requiring less computational complexity. Both LDPC codes and turbo codes with iterative decoding are seen to be robust to mark edge jitter     

基于多重置换阵的满秩结构化LDPC码构造方法

 在多重置换阵的基础上,提出一种适用基于网络编码的协作中继策略的结构化LDPC码构造方法.首先定义了多重置换阵的概念,提出并证明了该方阵在秩和消元等方面的重要性质;给出具体的构造步骤,构造了列重为3和围长至少为6的满秩LDPC码;分析了该LDPC码的生成矩阵,具有稀疏和结构化的特点,适用基于网络编码的协作中继系统中进行联合网络编码和迭代译码.仿真结果表明,在相同码长、2/3码率和准循环矩阵 Y 结构条件下,相比阵列LDPC码、近似双对角形式的LDPC码和三对角形式的LDPC码,新构造的LDPC码具有相对较好的译码性能.     

瑞利衰落信道下基于LDPC码USTM的MIMO系统

研究了一种联合低密度校验(LDPC,Low-Density Parity-Check)码和酉空时调制(USTM,Unitary Space-Time Modulation)技术在不相关瑞利平坦衰落(Rayleigh flat fading)下的多输入多输出信道(MIMO,Multiple-Input Multiple-Output)系统的性能.在无信道状态信息下,采用可并行操作的和积译码算法(SPA,Sum-Product Algorithm)的LDPCC-USTM级联系统具有优异的性能,并分析了不同LDPC码集下对系统性能的影响.仿真结果表明LDPCC-USTM级联系统比与未级联的相比有近23dB的编码增益,与基于Turbo码的USTM[6]系统相比有5dB多的编码增益,且基于非规则的LDPC码的级联系统比基于规则码有近1dB的编码增益.     

HIGH-PERFORMANCE SIMPLE-ENCODING GENERATOR-BASED SYSTEMATIC IRREGULAR LDPC CODES AND RESULTED PRODUCT CODES

Low-Density Parity-Check (LDPC) code is one of the most exciting topics among the coding theory community.It is of great importance in both theory and practical communications over noisy channels.The most advantage of LDPC codes is their relatively lower decoding complexity compared with turbo codes,while the disadvantage is its higher encoding complexity.In this paper,a new ap- proach is first proposed to construct high performance irregular systematic LDPC codes based on sparse generator matrix,which can significantly reduce the encoding complexity under the same de- coding complexity as that of regular or irregular LDPC codes defined by traditional sparse parity-check matrix.Then,the proposed generator-based systematic irregular LDPC codes are adopted as con- stituent block codes in rows and columns to design a new kind of product codes family,which also can be interpreted as irregular LDPC codes characterized by graph and thus decoded iteratively.Finally, the performance of the generator-based LDPC codes and the resultant product codes is investigated over an Additive White Gaussian Noise (AWGN) and also compared with the conventional LDPC codes under the same conditions of decoding complexity and channel noise.     

IEEE802.16e标准LDPC译码器设计与实现

LDPC码自在上个世纪90年代被重新发现以来,以其接近香农极限的差错控制性能,以及译码复杂度低、吞吐率高的优点引起了人们的关注,成为继Turbo码之后信道编码界的又一研究热点。利用FPGA设计并实现了一种基于IEEE802.16e标准的LDPC码译码器。该译码器采用偏移最小和（Offset Min-Sum）算法,其偏移因子β取值为0.125,具有接近置信传播（Belief Propagation）算法浮点的性能。译码器在结构上采用了部分并行结构,可以灵活支持标准中定义的所有码率和码长的LDPC码的译码。此外,该译码器还支持对连续输入的数据块进行处理,并具有动态停止迭代功能。硬件综合结果表明,该译码器工作频率为150MHz时,固定15次迭代,最低可达到95Mb/s的译码吞吐率,完全满足802.16e标准的要求。     

Accumulate-Repeat-Accumulate Codes

In this paper, we propose an innovative channel coding scheme called accumulate-repeat-accumulate (ARA) codes. This class of codes can be viewed as serial turbo-like codes or as a subclass of low-density parity check (LDPC) codes, and they have a projected graph or protograph representation; this allows for high-speed iterative decoding implementation using belief propagation. An ARA code can be viewed as precoded repeat accumulate (RA) code with puncturing or as precoded irregular repeat accumulate (IRA) code, where simply an accumulator is chosen as the precoder. The amount of performance improvement due to the precoder will be called precoding gain. Using density evolution on their associated protographs, we find some rate-1/2 ARA codes, with a maximum variable node degree of 5 for which a minimum bit SNR as low as 0.08 dB from channel capacity threshold is achieved as the block size goes to infinity. Such a low threshold cannot be achieved by RA, IRA, or unstructured irregular LDPC codes with the same constraint on the maximum variable node degree. Furthermore, by puncturing the inner accumulator, we can construct families of higher rate ARA codes with thresholds that stay close to their respective channel capacity thresholds uniformly. Iterative decoding simulation results are provided and compared with turbo codes. In addition to iterative decoding analysis, we analyzed the performance of ARA codes with maximum-likelihood (ML) decoding. By obtaining the weight distribution of these codes and through existing tightest bounds we have shown that the ML SNR threshold of ARA codes also approaches very closely to that of random codes. These codes have better interleaving gain than turbo codes     

基于二分图的乘积码迭代译码算法

该文给出了由汉明分量乘积码构造广义低密度(GLD)码的一般方法。基于所得稀疏矩阵的二分图,并结合分组码与低密度校验(LDPC)码的译码算法,设计出一种新颖的可用于乘积码迭代译码的Chase-MP算法。由于所得二分图中不含有长度为4和6的小环,因而大大减少图上迭代时外信息之间的相关性,进而提高译码性能。对加性高斯白噪声(AWGN)及瑞利(Rayleigh)衰落信道下,汉明分量 (63,57,3)2 乘积码的模拟仿真显示,该算法能够获得很好的译码性能。与传统的串行迭代Chase-2算法相比,Chase-MP算法适合用于全并行译码处理,便于硬件实现,而且译码性能优于串行迭代Chase-2算法。