基于Simulink的雷达视频积累仿真与分析

建立了基于Simulink的串联双回路积累器和双极点积累器的雷达视频积累仿真模型,分析了视频积累器参数与输出信噪比的关系,并给出了视频积累器对脉冲串的积累仿真结果。     

基于电荷耦合器件的电视信号增强器

电荷耦合器件是一种发展前景良好的半导体集成电路,该电路可用于彩色成像、信号处理等相关领域.文章介绍一种用CCD321型电荷藕合器件设计的视频信号积累器,目的在于探讨使用这种器件做视频信号积累的可行性.以电视视频信号处理为平台,研究视频色度信号的积累结果.实践证明,用这种器件设计的视频信号积累器能增强视频信号的信噪比,是一种理想的视频信号处理器件.     

基于凸优化的最小旁瓣恒定束宽时域宽带波束形成

 提出了基于凸优化的适用于任意结构基阵的最小旁瓣恒定束宽时域宽带波束形成方法.首先将基阵波束响应表达成一组有限脉冲响应(FIR)滤波器权值的线性函数,然后采用基于恒定束宽限制条件的最小旁瓣优化准则设计FIR滤波器权值.同时对滤波器系数进行范数约束以及对干扰方向设置展宽零陷来提高波束形成器的鲁棒性.将期望波束响应的设计过程与实际波束响应的逼近过程融合在一起进行优化搜索,获得了全局最优解.该波束形成器设计问题被转化成凸优化问题求解,仿真结果验证了所提方法的有效性.     

用滤波器组构成的传送多路复用器结构实现MMSE盲信道均衡

冗余滤波器组构成的传送多路复用器可以用来对FIR信道进行估计和均衡.本文提出一种在FIR滤波器组框架结构下,首先利用信号的相关矩阵对信道进行估计,然后在此基础上用MMSE准则下设计的FIR均衡器对数据进行均衡的盲算法.该均衡算法的性能要明显好于基于ZF准则的方法,并且在消除ISI的同时可以抑制噪声的影响,从而使系统的输出信噪比达到最优,而增加的复杂度很有限.文中最后在两种典型信道下对所提出的盲信道均衡算法进行了仿真,结果验证了上述性能.     

基于全相位陷波器解析设计的啸叫去除

为了快速且精准地抑制助听器中的啸叫效应,该文提出一种中心频率可以精确控制的全相位有限脉冲响应(FIR)陷波器解析设计.首先,为了获得较高的陷波精度,引入了整数部分m和小数部分λ来控制陷波的中心频率.然后,设计了一个偶对称的闭式解析式来计算陷波器系数.最后,为了保证输出信号的连续性和线性相位,进行数据延拓和截取操作.该陷波器具有线性传输特性,避免了非线性失真.为了检验陷波器的滤波性能,将其应用在助听器中去除啸叫.实验结果表明,该滤波器在啸叫频率下的衰减值可达–330 dB,信噪比达22 dB,输出波形质量好,算法复杂度低,鲁棒性高,具有一定的应用前景.     

基于广义旁瓣对消器的Laguerre宽带波束形成

基于Frost 结构的Laguerre 宽带波束形成器可以获得比FIR 宽带波束形成器和IIR 宽带波束形成器更好的性能,但其需要单极点的最优求解过程,存在计算复杂度较高及收敛速度较慢等问题.该文提出一种基于广义旁瓣对消器(Generalized Sidelobe Canceller, GSC)的Laguerre 滤波器宽带波束形成算法.该算法首先建立基于GSC结构的Laguerre 宽带波束形成器模型,然后利用最小二乘方法给出一种低复杂度的极点求解方法,最后利用归一化最小均方根误差方法实现宽带波束形成.仿真实验及理论分析表明,该方法无需基于Frost 结构的Laguerre 宽带波束形成器单极点最优求解过程,在保证算法较高的输出信干噪比的同时,减少了计算复杂度,提高了收敛速度.      

卫星导航接收机时域窄带干扰抑制滤波器设计与性能分析

针对卫星导航接收机时域窄带干扰的有效抑制问题,本文首先给出二阶格型IIR陷波器参数设计方法,通过陷波带宽的定量调整,既可以有效抑制窄带干扰,又可以降低卫星信号的失真;其次推导了二阶IIR格型陷波器相关输出信干噪比改善因子的闭合表达式,该表达式相比干扰抑制后信干噪比的改善,更为直观地反映了陷波器对卫星导航信号的影响。理论分析和仿真实验,二阶格型IIR陷波器相关输出信干噪比改善因子与陷波器的带宽参数有关,而与陷波频率无关,且二阶格型IIR陷波器的性能优于最优线性预测Wiener滤波器、最优线性插值Wiener滤波器、五系数FIR滤波器以及二阶直接型IIR陷波器。      

基于MATLAB与QUARTUS Ⅱ的FIR滤波器设计与验证

FIR滤波器是一种应用广泛的基本数字信号处理元件.针对常用的FIR滤波器设计方法存在的问题,采用MATLAB、QUARTUS Ⅱ设计实现16阶低通FIR滤波器,并通过仿真及实际测试验证该设计方案的正确性.相对于传统的设计方案,此设计方案能够直观检验滤渡器的设计效果,并且更方便,灵活,实用.     

FIR滤波器的FPGA高效实现和巧妙验证

为了降低FIR滤波器对FPGA资源的消耗,同时能够直接验证其滤波性能,本文介绍了基于加法器网络的FIR滤波器的实现方法,以及系数的CSD码、最优CSD码表示方法,并引出了更加高效的简化加法器网络法.以一个32阶FIR低通滤波器的实现为例说明了设计的过程,巧妙结合MATALB与QuartusⅡ对所设计的滤波器进行了验证.实践表明,该方法节约资源,调试方便.     

基于FPGA的FIR滤波器高效实现

本文针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行研究,首先给出了将乘法转化为查表的DA算法,然后简要介绍整数的CSD表示和我们根据FPGA实现要求改进的最优表示;接着,本文讨论了在离散系数空间得到FIR滤波器系数最优解的混合整数规划方法;最后采用这一方法设计了最优表示离散系数FIR滤波器,通过FPGA仿真验证这一方法是可行的和高效的.     

Digital integrator design using Simpson rule and fractional delay filter

The IIR digital integrator is designed by using the Simpson integration rule and fractional delay filter. To improve the design accuracy of a conventional Simpson IIR integrator at high frequency, the sampling interval is reduced from T to 0.5T. As a result, a fractional delay filter needed to be designed in the proposed Simpson integrator. However, this problem can be solved easily by applying well-documented design techniques of the FIR and all-pass fractional delay filters. Several design examples are illustrated to demonstrate the effectiveness of the proposed method.     

FIR filter design over discrete coefficients and least square error

The difference routing digital filter (DRDF) consists of an FIR filter followed by a first-order integrator. This structure with power-of-two coefficients has been studied as a means of achieving low complexity, high sampling rate filters which can be implemented efficiently in hardware. The optimisation of the coefficients has previously been based on a time-domain least-squares error criterion. A new design method is proposed that includes a frequency-domain least-squares criterion with arbitrary frequency weighting and an improved method for handling quantisation of the filter coefficients. Simulation studies show that the new approach yields an improvement of up to 7 dB over existing methods and that oversampling can be used to improve performance     

基于改进的Tustin算子的分数阶数字积分器设计

根据传统的Tustin积分算子的积分原理,改变Tustin积分算子的采样间隔,提高积分精度,以此得到了改进的新算子,然后通过Lagrange FIR分数阶延迟滤波器把新积分算子中的分数阶项转换为整数阶,最后采用连续分数展开(CFE)的方法实现了分数阶数字积分器设计.实验证明,设计的分数阶数字积分器在幅频特性上面明显优于传统方法设计的分数阶数字积分器.     

Using fractional delay to control the magnitudes and phases of integrators and differentiators

The use of fractional delay to control the magnitudes and phases of integrators and differentiators has been addressed. Integrators and differentiators are the basic building blocks of many systems. Often applications in controls, wave-shaping, oscillators and communications require a constant 90deg phase for differentiators and -90deg phase for integrators. When the design neglects the phase, a phase equaliser is often needed to compensate for the phase error or a phase lock loop should be added. Applications to the first-order, Al-Alaoui integrator and differentiator are presented. A fractional delay is added to the integrator leading to an almost constant phase response of -90deg. Doubling the sampling rate improves the magnitude response. Combining the two actions improves both the magnitude and phase responses. The same approach is applied to the differentiator, with a fractional sample advance leading to an almost constant phase response of 90deg. The advance is, in fact, realised as the ratio of two delays. Filters approximating the fractional delay, the finite impulse response (FIR) Lagrange interpolator filters and the Thiran allpass infinite impulse response (IIR) filters are employed. Additionally, a new hybrid filter, a combination of the FIR Lagrange interpolator filter and the Thiran allpass IIR filter, is proposed. Methods to reduce the approximation error are discussed.     

粒子群优化算法在FIR数字滤波器设计中的应用

本文针对有限脉冲响应(FIR)数字滤波器的设计实质上是一个多参数优化问题,提出了一种用粒子群优化算法(PSO)设计FIR数字滤波器的方法.首先将滤波器的设计问题转化为滤波器参数的优化问题,然后利用粒子群优化算法对整个参数空间进行高效并行搜索以获得参数的最优化.FIR数字低通、带通滤波器设计实例证明了该方法的有效性和优越性.     

On design of a novel class of selective CIC FIR filter functions with improved response

The Cascaded-Integrator-Comb (CIC) filter is a non-recursive (FIR) filter which is multiplier free, consisting only of two building blocks (simple integrator stage and simple comb filter stage) and has a linear phase. This paper summarizes some key points of classical CIC filters and proposes a novel class of CIC FIR filter functions. A novel class of CIC filter functions maintains simplicity of FIR filters by avoiding the multipliers, but shows excellent performances in term of insertion loss in stopband and selectivity with respect to conventional CIC filters. A set of simulations along with illustrative examples is conducted in order to compare the attenuation characteristics of the classical CIC filter functions and the proposed novel class of selective CIC FIR filter functions. For the same level of a constant group delay τ = 45.5 s, a classical CIC filter function has insertion loss of 166.3 dB, and designed novel filter function has a higher level of insertion loss 206.55 dB.     

Method for FIR filters design with compressed cosine using Chebyshev's norm

This paper considers a new method for FIR filters design. The method uses an L_∞ optimality norm. To achieve a better approximating effect, a new modulating function which compresses the oscillations of the cosine is proposed. A parameter sets the gradient of the modulating function, with respect to the oscillations’ compression. The approximating polynomial is carried out using Remez’ exchange algorithm. An optimal polynomial with lowest possible (four) degree, that approximates an ideal filter's response with high precision is proposed. With the proposed method a FIR filter with arbitrary specifications can be designed. Design examples of FIR filters with a minimization of calculation are performed. The obtained filter's responses are close to the ideal response. The design examples demonstrate that the proposed approach may be a good alternative in several applications.     

Design of digital FIR variable fractional order integrator and differentiator

This paper presents an easy and simple method to design variable fractional order digital FIR integrators and differentiators based on fractional order systems. First, closed-form digital IIR fractional order integrators and differentiators have been obtained from the analog rational functions approximations, in a given frequency band, of the fractional order integrator s ^?m and differentiator s ^m (0?<?m?<?1) through the Tustin generating function. Then, closed-form digital FIR fractional order integrators and differentiators by truncation of the digital IIR ones have been derived. Next, polynomial interpolation has been used to design digital FIR variable fractional order integrators and differentiators that can be implemented by the Farrow structure. The main feature of variable fractional order operator is that its order can be changed without re-designing a new fractional order operator. Some examples have been presented through the paper to illustrate the performance and the effectiveness of the proposed design method. The results obtained have been discussed and have been compared to one of the most recent works in the literature using the same design parameters.     

High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.