i860微处理器页方式DRAM及其控制器的设计

在微处理机系统中，存储器的访问速度对微处理器性能的发挥有极大的影响。本文给出了以ｉ８６０为微处理器的页方式ＤＲＡＭ设计方案，以比较简单的控制线路来提高ＤＲＡＭ的访问速度．     

专家评述半导体周期与市场

多年来，由于DRAM在芯片工业中的特殊地位，在半导体周期中备受关注。据美国SIA宣布，1997年微处理器的总销售额首次超过DRAM但是，有关专家认为目前对半导体市场的影响不是最大便是很大的仍然是DRAM。DRAM的总销售额仍将不断冲击未来十年的半导体工业。根据DRAM对半导体市场的     

降低系统LSI批量生产测试成本

对于内置DRAM的ASIC,可以采用总线隔离测试、BIST及扫描测试等方法;对于内置DRAM的微处理器,可以利用微处理器仿真执行存储器测试仪的硬件功能进行测试。     

国际新闻

世界半导体市场 动向与展望 据报道,目前各半导体厂家正在向高速DRAM过渡,加强快闪存储器生产。16M DRAM的需求旺盛,以EDO和同步型等高速存储器为主。4M DRAM的产量会由于降价的影响而减少,厂家下半年将以生产16M DRAM为主。 微处理器和专用IC也在向     

DRAM正朝着多元化方向发展

<正> 通常,DRAM 是廉价、标准的存储器代表,微处理器速度的不断提升和网络设施及器件的日益发展,都需要大量的 DRAM。一般来说,廉价的内存意味着标准的 DRAM 被工业界所接受。但是,这样     

智能电话机

<正> 现代社会已进入信息时代。信息技术日新月异。微处理器和存储器集成芯片正在应用于电话机中,使之向多功能、智能化方向发展。 下面以HL—946电话机为例,介绍智能电话机的组成及工作原理。 HL—946数字录音电话的构成如图1所示。它由微处理器(DSP)、存储软件的可编程只读存储器(EPROM)、存储语音的动态随机存储器(DRAM)、编码/解码器及外围电路组成。模—数转换器(ADC)对语音信号进行每秒8000次采样。获得的数字信号经过微处理器加工处理后,被压缩在DRAM中;放音时,微处理器把DRAM中的信息调出进行解码、合成,最后通过数—模转换(DAC)获得语音。微处理器采用的是美国最先进的ADSP集成芯片,它调用和执行EPROM中的软件,从而完成所有的计算和处理工作。它能接受外部命令(按键)而     

SDRAM器件发展动向

Internet应用日益深入普及,极大地推动电子元器件市场和技术发展。PC机的CPU芯片微处理器时钟频率已跨入GHz领域,打印机和显示器的工作速度也迅速提高。作为PC机的主存储器用器件,DRAM的存取速度空前提高,而且新品种层出不穷,同步DRAM(SDRAM)、Rambus DRAM乃至双倍数据速率同步DRAM(简称DDR),争奇斗艳。     

厂商动态

Intel公司将其产品从存储器转向微处理器以来,10年间销售额增长近五倍之多.如今,该公司在拥有年增长率高达30%的微处理器产品的同时,又打算开拓新的业务领域.开展微处理器竞争费用高昂80年代中期,由于日本半导体厂家的追逼,Intel公司毅然决定进行以本企业生命作赌注的大改革——退出DRAM市场,专攻微处理器.     

最新计算机高速动态存储器

多媒体的发展使计算机的功能不断增加。图像处理时不可或缺的高速、大容量存储器就成了和微处理器同等重要的器件。 本文将重点介绍日益受到人们关注,在计算机中作图像处理的高速动态存储器(DRAM)新品:EDODRAM、SDRAM和Rambus公司的DRAM。照片1为三种高速DRAM的封装。     

微处理器·数字信号处理器·微控制器

含DRAM的16位微处理器 Infincon Technologies的16位微处理器C163-24D的性能为33 MHz、其中包含192kB的DRAM,工作在3.3 V也可以工作在5V,功耗低于300 mW。用于手提电脑和台式电脑的硬盘机、电信、临控及数据采集,移动网络设备。封装:100脚TQFP,引脚与该公司其它C163及C165微控制器相同。网址:http//www.infineon.com     

Hidden double data transfer scheme for MDL design [merged DRAMlogic]

A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 μm DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory     

内存条的结构与应用研究

采用大容量的存储器扩大单片机数据空间，常用的器件有：RAM、FLASH RAM、NVRAM以及DRAM。其中，DRAM具有容量特点大、价格低的优点。介绍了内存条的刷新原理和工作时序，详细讨论了89C51单片机与内存条接口设计的方法。最后采用ispLSI1032进行了集成处理，简单可靠，可使单片机系统拥有大容量的数据存储空间。     

基于FPGA技术的DRAM分时存取方法

介绍了一种基于现场可编程技术对DRAM进行读写和刷新操作的方法，根据现场可编程器件设计的特点，结合DRAM读写和刷新时序的要求，提出了同步化操作DRAM的思想，给出了具体同步化操作DRAM的实现方法，针对现场可编程器件设计中经常有多模块同时存取DRAM芯片的需求，提出了对DRAM芯片进行分时存取的方法，讨论了该方法的实现机制，结合具体的项目设计，给出了分时存取方法的关键时序，避开了复杂的DRAM控制器，节省了设计资源，简单方便地解决了DRAM操作的仲裁问题。     

TLM: a trench leakage monitor for a four megabit SPT DRAMtechnology

The authors discuss a single trench capacitor macro-array structure used for trench dynamic random access memory (DRAM) device design and characterization, and as a manufacturing test vehicle. A nonaddressable array of trench-capacitor DRAM cells is used for quantification of trench DRAM leakage parameters, storage node parasitic device characterization, and silicon defects. Used with an addressable functional monitor, it is found to be a valuable semiconductor process development vehicle to achieve functionality and cell retention yield for a 4-Mb CMOS DRAM technology     

A 4-Mbit DRAM with half-internal-voltage bit-line precharge

A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-/spl mu/m minimum design rule. As a result, a 4M word/spl times/1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-/spl mu/m/SUP 2/ storage cells.     

A 256-Mb SDRAM using a register-controlled digital DLL

This paper describes the key technologies used in a 256-Mb synchronous DRAM with a clock access time of 1 ns. This DRAM is stable against temperature, voltage, and process variation through the use of a register-controlled digital delay-locked loop (RDLL). The total timing error of the RDLL is about 0.4 ns, sufficient for high frequency operation at 150 to 200 MHz. Unlike most conventional high-density DRAMs, the bit lines are placed above the storage capacitors in this DRAM to relax the design rules of the core area. The noise issues were analyzed and resolved to help implement the technology for mass production of 0.28- to 0.24-μm 200-MHz DRAMs     

An experimental 1-Mbit cache DRAM with ECC

A cache DRAM which consists of a dynamic RAM (DRAM) as main memory and a static RAM (SRAM) as cache memory is proposed. An error checking and correcting (ECC) scheme utilizing the wide internal data bus is also proposed. It is constructed to be suitable for a four-way set associated cache scheme with more than a 90% hit rate estimated to be obtained. An experimental cache DRAM with 1-Mb DRAM and 8-kb SRAM has been fabricated using a 1.2-μm, triple-polysilicon, single-metal CMOS process. A SRAM access time of 12 ns and a DRAM access time of 80 ns, including an ECC time of 12 ns, have been obtained. Accordingly, an average access time of 20 ns is expected under the condition that the hit rate is 90%. The cache DRAM has a high-speed data mapping capability and high reliability suitable for low-end workstations and personal computers     

Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer

A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped poly-Si TSVs were used for vertical traces inside silicon and interconnection between DRAM chips to realize a DRAM-compatible process. Through optimization of process conditions and layout design, a fast poly-Si filling has been obtained. The entire packaging was carried out at the wafer level by using smart chip connection with feedthrough interposer (FTI) technology. A new bump and wiring structure for the FTI has also been developed for fine-pitch and low-cost bonding. Normal operation during DRAM read/write was confirmed on a 512-Mb DRAM with TSVs, with an I/F chip as a memory controller. Simulation and measurement of the transfer function of the FTI wiring showed a 3-Gb/s/pin data transfer capability.     

An access-sequence control scheme to enhance random-accessperformance of embedded DRAM's

An embedded DRAM enables a high data-transfer rate since it provides an on-chip wide-bus interconnection. However, the net data-transfer rate is reduced by page misses because of the inherently large row-access time of DRAM's. We previously proposed a multibank DRAM macro based on a micromodule architecture to overcome this problem. The pipelined access of the DRAM macro is especially useful for regular access in graphics applications. In this paper, we propose an access-sequence control scheme which enhances the random-access performance of embedded DRAMs. Access ID numbers, an access queue register, and a write-data buffer combined with the multibank DRAM enable out-of-sequence access which reduces the page-miss penalty during random access. In the case of four successive accesses, the estimated total access time was, respectively, reduced by up to 38 and 32% for one and two page misses, and for five successive accesses with one or two page misses, it was, respectively, reduced by up to 44 and 45%     

Measurement of transient effects in SOI DRAM/SRAM accesstransistors

Bitline-induced transient effects in access transistors pose a problem in SOI DRAM and SRAM cells. The floating-body potential is affected by the bitline so changes in the bitline potential may upset the charge stored in the memory cell. Transient effects in SOI access transistors are measured versus the time the bitline is at high voltage, and V_DD for fully- and partially-depleted SOI devices. Bulk devices show no bitline-induced transient effects. Measurements show that the magnitude of the charge upset can be large enough to disturb the charge stored in DRAM and SRAM cells. Measurements also show that for any substantial upsets to occur, the time the bitline has to be at high voltage is on the order of milliseconds. Although the effect of bitline transitions is cumulative, the amount of charge upset when the bitline switches rapidly (i.e., millisecond periods) is shown to be negligible. Thus, proper design of SRAM upset-charge protection and DRAM refresh time should circumvent this problem