共查询到17条相似文献,搜索用时 453 毫秒
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按频率抽取的基4FFT算法在FPGA中实现 总被引:2,自引:0,他引:2
雷达成像的数据处理运算量非常巨大,要达到准实时甚至全实时的成像处理速度,就需要高性能的处理设备。结合自己的工程实践,介绍了按频率抽取的基4 FFT算法在FPGA器件中的实现。基于高速FPGA的SAR实时信号处理机是该系统的核心部分,这方面的研究国内才刚刚起步,该文的工作对SAR雷达系统的硬件实现具有重要意义,为SAR实时成像处理提供了一条有效途径,具有良好的应用前景,此技术的实现在实时信号处理领域也具有重要意义。 相似文献
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针对合成孔径雷达实时成像处理中数据量大、数据吞吐率高、成像算法实现复杂等特点,设计了适合于无人机载SAR实时信号处理系统的硬件平台和实时信号处理算法流程。该信号处理系统包括一块带有AD采集功能的接口板和两块以TS201为核心处理器的信号处理板。考虑到实时性要求和无人机平台的不稳定性,设计了一种结合惯导和回波数据进行运动补偿的改进型RD成像算法。在无人机平台上成功稳定地实现大面积连续实时成像,证明信号处理系统稳定可靠,实时信号处理算法可行。 相似文献
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用ADSP21062高速信号处理系统实现机载SAR实时成像处理器的方位向处理 总被引:1,自引:0,他引:1
机载SAR实时成像处理器可以在载机飞行的同时获得高分辨率的SAR图像,对于实时监测、军事侦察等应用具有重要意义。实时成像处理器就是用高速数字信号处理系统来实时地实现SAR的成像算法。该文介绍SAR实时成像处理器方位向处理部分的研制,该部分采用了自行开发的、基于ADSP21062的高速信号处理系统,8片ADSP21062被安排在4个并行处理通道中,具有960MFLOPS的峰值处理速度,优化的软件设计保证了硬件资源的利用效率。仿真测试和外场实验证明了该系统的设计是成功的。该文对方位向处理部分的实现原理、硬件结构、软件设计进行了详细介绍。 相似文献
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在分析ISO18000-6C标准内容的基础上,提出了一种基带处理器的结构,设计了一款符合ISO18000-6C标准的UHF RFID标签芯片的基带处理器。该基带处理器可支持协议规定的所有强制命令。设计通过降低工作电压、降低工作频率、使用门控时钟、增加功耗管理模块等一系列低功耗设计以降低处理器的功率消耗。在Xillinx的Virtex-4FPGA上验证满足协议功能要求,并在工作电压为1V,时钟为1.92MHz时,功耗仿真结果为9.9μW,很好的完成了低功耗电子标签的基带处理器设计。 相似文献
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Hai Li Bhunia S. Yiran Chen Roy K. Vijaykumar T.N. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(3):245-254
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which effectively reduces clock power. DCG is based on the key observation that for many of the pipelined stages of a modern processor, the circuit block usage in the near future is known a few cycles ahead of time. Our experiments show an average of 19.9% reduction in processor power with virtually no performance loss for an eight-issue, out-of-order superscalar by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers. 相似文献
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Lennart Yseboodt Michael De Nil Jos Huisken Mladen Berekovic Qin Zhao Frank Bouwens Jos Hulzink Jef Van Meerbergen 《Journal of Signal Processing Systems》2009,57(1):107-119
Wireless sensor nodes span a wide range of applications. This paper focuses on the biomedical area, more specifically on healthcare
monitoring applications. Power dissipation is the dominant design constraint in this domain. This paper shows the different
steps to develop a digital signal processing architecture for a single channel electrocardiogram application, which is used
as an application example. The target power consumption is 100 μW as that is the power energy scavengers can deliver. We follow
a bottleneck-driven approach: first the algorithm is tuned to the target processor, then coarse grained clock-gating is applied,
next the static as well as the dynamic dissipation of the digital processor is reduced by tuning the core to the target domain.
The impact of each step is quantified. A solution of 11 μW is possible for both radio and DSP running the electrocardiogram
algorithm.
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Jef Van MeerbergenEmail: |
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Low-power design for embedded processors 总被引:1,自引:0,他引:1
Moyer B. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》2001,89(11):1576-1587
Minimization of power consumption in portable and battery powered embedded systems has become an important aspect of processor and system design. Opportunities for power optimization and tradeoffs emphasizing low power are available across the entire design hierarchy. A review of low-power techniques applied at many levels of the design hierarchy is presented, and an example of low-power processor architecture is described along with some of the design decisions made in implementation of the architecture 相似文献