微波功率晶体管的热失效分析

微波功率晶体管是微波功率放大器中的核心器件,其热性能在很大程度上决定于封装管芯的管壳.针对某型号的微波功率晶体管在进行生产筛选的功率老化试验时出现的热失效问题进行分析与讨论,最终确定器件管壳内用于烧结管芯的氧化铍(BeO)上的多层金属化层存在质量缺陷,使管芯到BeO的热阻增大,因此出现了老化时部分器件失效现象.提出了预防措施,既可避免损失,也能保证微波功率晶体管在使用中的可靠性.     

使用金锡合金焊接微波功率GaAs MESFET管芯

微波功率GaAsMESFET的结构是在半绝缘砷化镓衬底上外延生长n型薄层砷化镓,然后在其上做源、漏欧姆接触和肖特基势垒栅.我们通过管芯侧面和背面金属化实现了大面积源接地.器件对管芯焊接工艺的基本要求是:(1)低温焊接;(2)导电导热性能良好;(3)可靠性高;(4)成品率高等等.我们曾经试用工艺比较成熟的银浆烧结(烧结温度是370℃),但是发现部分管芯特性变坏和焊接不牢、热阻大、串联电阻大以及工艺重复性差等问题.经过分析,我们认为高的导热率和高的电导率是     

半导体激光器可靠性设计考虑

简述了半导体激光器可靠设计中的模式控制设计、管芯芯片的晶格匹配、结构设计、管芯芯片的金属化（欧姆接触）设计，以及器件的金属化气密封装设计等的设计考虑。     

金属化工艺对开关晶体管工作可靠性的影响

文本文对在工作过程中损坏的开关晶体管的解剖结果进行了分析 ,发现管芯正背面金属膜质量是引起开关晶体管失效的重要原因之一 ,指出正背面金属化工艺过程中应注意的几个问题     

硅功率管芯片背面金属化结构研究

本文分析了硅功率管管芯背面金属处理的结构设计原则,介绍了用多层金焊薄膜(Au/Ni/Cr)作为新的金属化处理方案及实际使用效果,以有助于国产管芯背面处理方案的改进     

金属化工艺对开关晶体管应用可靠性的影响

本对在工作过程中损坏的开关晶体管的解剖结果进行了分析，发现管芯正背面金属膜质量是引起开关晶体管失效的重要原因之一，指出正背面金属化工艺过程中应注意的几个问题。     

功率晶体管管芯背面多层金属电极工艺

以功率晶体管ＢＵ４０６管芯为例采用背面多层电极工艺，大大提高了器件的抗热疲劳性、稳定性和可靠性。产品合格率和间歇工作寿命均达到了国内外同类产品的先进水平     

功率是昌体管管芯背面多层金属电极工艺

以功率晶体管ＢＵ４０６管芯为例采用背面多层电极工艺，大大提高了器件的抗热疲劳性、稳定性和可靠性。产品合格率和间歇工作寿命均达到了国内外同类产品的先进水平。     

表面电场对3DK9开关晶体管可靠性影响的研究

针对3DK9开关晶体管在应用中出现表面漏电失效的具体案例进行分析研究.该器件的设计在基极场板边缘处同时出现金属化台阶和表面尖峰电场,这是影响器件可靠性的重要因素.针对原器件结构的缺陷,提出了一种新的器件结构,即采用结终端扩展技术代替基极场板.新结构不仅大大降低了表面尖峰电场,而且避免了金属化台阶与高电场出现在同一区域的情况,从而提高了器件可靠性.     

半导体器件氦检漏报告

近年来,半导体器件和集成电路发展很快,其应用也日益广泛.对其可靠性和稳定性也相应地提出了新的要求.为极大程度地消除由于器件封装漏气使管芯暴露于潮气等各种有害气氛中所导致器件电性能劣化或失效之因素,研究半导体器件和电路封装的气密性,就成为当前和今后不可低估的工作了.     

Morphological and electrical comparison of Ti and Ta based ohmic contacts for AlGaN/GaN-on-SiC HFETs

The morphology and impact on leakage currents of two different ohmic metal stacks for GaN based transistor devices is investigated in this work. The results have implications for the performance and reliability of a GaN transistor device. A low temperature Ta based and a higher temperature anneal Ti based metallization are compared. The low temperature process shows a smoother metal semiconductor interface together with several orders of magnitude lower vertical and lateral leakage compared to the conventional higher temperature process. In addition to the leakage tests, back bias ramping experiments are performed unveiling potential advantages of the conventional approach in mitigating current collapse. However the low leakage will enable higher voltage operation making the low temperature process the preferable choice for high power RF applications, if simultaneously current collapse can be controlled.     

A metallization scheme for junction-down bonding of high-power semiconductor lasers

High-power semiconductor lasers have found increasing applications in industrial, military, commercial, and consumer products. The thermal management of high-power lasers is critical since the junction temperature rise resulting from large heat fluxes strongly affects the device characteristics, such as wavelength, kink power, threshold current and efficiency, and reliability. The epitaxial-side metallization structure has significant impact on the thermal performance of a junction-down bonded high-power semiconductor laser. In this paper, the influence of the epitaxial-side metal (p-metal) on the thermal behavior of a junction-down mounted GaAs-based high-power single-mode laser is studied using finite-element analysis. It is shown that a metallization structure with thick Au layer can significantly reduce the thermal resistance by distributing the heat flow to wider area laterally, and the thermal resistance of a junction-down bonded laser with thick Au metallization is much less sensitive to the voiding in the die attachment solder interface than a laser with thin Au metallization. A metallization structure of Ti-Pt-thick Au-Ti-Cr-Au is designed and implemented, and the metallurgical stability of this metallization scheme is reported. It was found that, without a diffusion barrier, the thick Au layer in the epi-side metallization would be mostly consumed and form intermetallics with the Sn from the AuSn solder during soldering and thermal aging. The Ti-Pt-thick Au-Ti-Cr-Au metallization scheme prevents the diffusion of Sn into the thick Au layer and preserves the integrity of the metallization system. It is a promising candidate for junction-down bonding of high-power semiconductor lasers for improved thermal management and reliability.     

Extended metallization reliability testing: Combining standard wafer level with product tests to increase test sensitivity

For future semiconductor technologies with larger interconnect aspect ratios, metallization is more prone to stress and electro migration. Therefore, metallization reliability is expected to become increasingly important. However, challenges arise if test structures and test methodologies are not accommodated to trace reliability issues with sufficient sensitivity. In such cases long test times and high volume tests are required to guaranty the metallization reliability. An extended test method is presented which addresses these problems by directly investigating the product at wafer level instead of a limited set of test structures. The method will be demonstrated for the example of stress migration in aluminum filled vias.     

Preparation and Temperature Cycling Reliability of Electroless Ni(P) Under Bump Metallization

The reliability of electroless Ni(P) under-bump metallization (UBM) was evaluated via temperature cycling and solder bump shear strength tests. Commercial diodes and dummy dies fabricated in-house were used as substrates for the electroless Ni(P) UBM deposition. Solder bumps were formed after reflowing eutectic 63Sn37Pb solder foils over the Ni(P) UBM. The solder bump shear strength was measured before and after different temperature cycling. The results from this study showed that the UBM thickness and dimension had important effects on the solder bump shear strength and reliability. Both the larger UBM dimension and larger UBM thickness tended to induce higher stress in the UBM, which resulted in the lower solder bump shear strength and lower temperature cycling reliability. A better UBM structure solution for high current electronic packaging application is indicated in this paper     

Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon

The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm$^{2}$) and the die size (approximately 15 mm$^{2}$ ) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.      

GLSI多层布线钨插塞CMP表面质量的影响因素分析

随着超大规模集成电路向高集成、高可靠性及低成本的方向发展,对IC工艺中的全局平坦化提出了更高的要求。在特大规模集成电路(GLSI)多层布线化学机械抛光(CMP)过程中,抛光质量对器件的性能有明显影响。研究了多层互连钨插塞材料CMP过程中表面质量的影响因素及控制技术,分析了抛光过程中影响抛光质量的主要因素,确定了获得较高去除速率和较低表面粗糙度的抛光液配比及抛光工艺参数。     

Reliability aspects of copper metallization and interconnect technology for power devices

The introduction of thick copper metallization and topside interconnects as well as a superior die attach technology is improving the performance and reliability of IGBT power transistor technologies significantly.The much higher specific heat capacity and higher thermal conductivity increases the short circuit capability of IGBTs, which is especially important for inverters for drives applications. This opens the potential to further optimize the electrical performance of IGBTs for higher energy efficiency.The change in metallization requires the introduction of a reliable barrier against copper diffusion and copper silicide formation. This requires the development of an efficient test method and reliability assessment according to a robustness validation approach.In addition, the new metallization enables interconnects with copper bond wires, which yield, together with an improved die attach technology, a major improvement in the power cycling capability.     

电子束蒸发工艺中源飞溅的控制

采用电子束蒸发进行的背面金属化工艺中遇到的较为常见的问题,就是在蒸发过程中发生的蒸发源飞溅状况。这是影响工艺可靠性及稳定性的重要问题,如何通过工艺控制手段减少甚至杜绝此类问题的出现对实际生产是很有指导性意义的。文中对该问题产生的原因进行分析并展开讨论,并提出了相关控制措施。     

Reliability issues of GaN based high voltage power devices

GaN based power devices for high efficiency switching applications in modern power electronics are rapidly moving into the focus of world wide research and development activities. Due to their unique material properties GaN power devices are distinguished by featuring high breakdown voltages, low on-state resistances and fast switching properties at the same time. Finally, these properties are the consequences of extremely high field and current densities that are possible per unit device volume or area. Therefore, in order to obtain very high performance, the material itself is stressed significantly during standard device operation and any imperfection may lead to wear out and reliability problems. Thus material quality, the specific epitaxial design as well as the device topology will directly influence device performance, reliability and mode of degradation. The paper will mainly discuss those degradation mechanisms that are especially due to the specific material combinations used in GaN based high voltage device technology such as epitaxial layer design, chip metallization, passivation schemes and general device topology and layout. It will then discuss technological ways towards engineering reliability into these devices. Generally, device designs are required that effectively minimize high field regions in the internal device or shift them towards less critical locations. Furthermore, an optimized thermal design in combination with suitable chip mounting technologies is required to enable maximum device performance.     

S波段大功率SiC MESFET的设计与工艺制作

针对SiC功率金属半导体场效应晶体管如何在实现高性能的同时保证器件长期稳定的工作,从金属半导体接触、器件制造过程中的台阶控制、氧化与钝化层的设计及器件背面金属化实现等方面进行了分析;并结合具体工艺,对比给出了部分实验结果。从测试数据看,研制的微波SiC MESFET器件性能由研制初期在S波段瓦级左右的功率输出及较低的功率增益和功率附加效率,达到了在实现大功率输出的条件下,比Si器件高的功率增益和30%以上的功率附加效率,初步体现了SiC MESFET微波功率器件的优势,器件的稳定性也得到了提升,为器件性能和可靠性的进一步提升奠定了设计和工艺基础。