共查询到19条相似文献,搜索用时 125 毫秒
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提出一种采用多输入浮栅MOS管设计具有可控阈值功能的电压型多值逻辑电路的方法.对每个浮栅MOS管的逻辑功能均采用传输开关运算予以表示以实现有效综合。在此基础上提出了一种新的电压型多输入浮栅MOS四值编码器和译码器设计。所提出的电路在结构上得到了非常明显的简化,并可采用标准的双层多晶硅CMOS工艺予以实现。此外,这些电路具有逻辑摆幅完整、延迟小等特点。采用TSMC0.35μm双层多晶硅CMOS工艺参数的HSPICE模拟结果验证了所提出设计方案的正确性。 相似文献
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基于0.6μmCMOS工艺设计了一种新型的pH值传感器。多晶硅和双层金属电极形成复合的悬浮栅结构,Si3N4钝化层作为敏感层。传感单元为W/L=500μm/20μm的PMOS管,其阈值电压随溶液pH值线性变化,并通过恒定PMOS管源漏电压和源漏电流控制电路转换成PMOS管源电压线性输出。PMOS管源电压线性输出范围达到4.6V,很好满足在不同pH值溶液中测试的要求。采用波长396nm紫外灯管照射来消除浮栅上电荷,增大阈值电压并有效调整溶液栅电压线性区工作范围。紫外照射后溶液栅电压可偏置在0V,减少溶液中噪声影响。CMOSpH值传感器的平均灵敏度为35.8mV/pH。 相似文献
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一种粒子探测器的CMOS读出电路设计 总被引:1,自引:0,他引:1
提出了新型的应用于粒子探测器CMOS读出电路中的电荷灵敏放大器和CR-(RC)n半高斯整形器的结构.电荷灵敏放大器采用多晶硅电阻做反馈来减小噪声,仿真发现与传统结构相比,在探测器电容高达150pF时,输入等效噪声电荷数由5036个电子减小到2381个,代价是输出摆幅减小了0.5V.在整形器中,MOS管电阻与多晶硅电阻串联,通过调节MOS管的栅压来改变阻值,以补偿工艺的偏差,在不明显降低线性度的情况下保证了时间常数能够比较精确控制. 相似文献
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通过对νMOS管特性和多值逻辑电路设计原理的研究,本文提出一种新型多值计数器的设计方案。该方案利用νMOS管具有多输入栅加权信号控制及浮栅上的电容耦合效应等特性,结合二值逻辑编码方法,实现电路的多值输出。用PSPICE对所设计的电路模拟验证,结果表明,所设计的电路逻辑功能正确,结构简单,功耗低,且通用性强,易于实现。 相似文献
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提出了一种适合低电源电压应用的新型MOS自举采样开关电路.通过“复制”自举电容和采样开关作为电荷损耗检测电路,并将检测出的电压降低值重新加到自举电容上,解决了传统MOS自举采样开关在低电源电压下工作时的电荷分享问题.基于0.18μm标准CMOS工艺,对电路进行了仿真.结果显示,在输入频率为60 MHz、峰-峰值为1V、采样频率为125 MHz时,与传统自举采样电路相比,新型自举采样电路采样开关管具有更低的导通电阻,无杂散动态范围( SFDR)提高了8dB,特别适合在低压高速A/D转换器中使用. 相似文献
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设计了一种应用于片外大电容场景下的具有快速瞬态响应特性的LDO。电路通过采用负载电流采样负反馈的结构构成了一个高带宽的电压缓冲器。该LDO使用具有电容倍增功能的共栅共源补偿结构,在外挂1μF负载电容的条件下,仅需500 fF的片上补偿电容即可保证在全负载范围内的稳定性。此外,通过使用自适应偏置技术,在减小轻载功耗的同时进一步提升了瞬态响应速度。电路采用0.18μm CMOS工艺进行设计与仿真验证。仿真结果表明,在LDO的输入电压为1.2 V、输出电压为1 V时,当负载电流以0.1μs的速度在150 mA和100μA之间切换时,最大电压变化仅为10.7 mV,输出电压恢复时间小于0.7μs。 相似文献
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This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V. 相似文献
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A new high-density multiple-valued content-addressable memory (CAM) is proposed to perform highly parallel search operations in a limited chip area. The number of cells in the CAM is reduced by the use of multiple-valued data representation. Moreover, multiple-valued stored data correspond to the threshold voltage of a floating-gate MOS transistor, so that the cell circuit can be designed using only a single transistor. As a result, the cell area of the proposed four-valued CAM is reduced to 14% of that of a conventional dynamic binary CAM, and its performance is about 5.4-times higher than that of the corresponding binary one under a 0.8-μm standard EEPROM technology 相似文献
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提出了一种新颖的可用于AC/DC控制芯片中的基准电压源电路。此电路以PTAT(proportional to absolutetemperature)电流为偏置电流,利用二极管连接的MOS晶体管迁移率和阈值电压的温度系数可相互补偿的特性,产生与温度无关的栅源电压。该电路结构简单,既无启动电路也无运放,避免了运放失调对基准源的影响,设计采用CSMC0.5μm BCD工艺。仿真结果表明,该基准电压源具有较低的温度系数和高电源电压抑制比,可作为AC/DC控制芯片中迟滞比较器的参考源。 相似文献
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Kwang Ming Lin CheeYee Kwok Ruey Shing Huang 《Electron Device Letters, IEEE》1996,17(5):247-249
A prototype of a new thermo-capacitive integrated flow sensor consisting of a floating-gate MOS transistor has been developed. Tantalum pentoxide is the dielectric material between the top (control) gate and the floating-gate. The temperature dependence of the dielectric constant is about 375 ppm/°C. The process flow is compatible with standard MOS process and augmented to include a capacitor module and bulk micromachining. The output voltage change at the flow velocity of 20 m/s is about 26 mV at 57 mW of heater power. The sensitivity in the 0-4 m/s flow velocity region is 4.25 mV(m/s)-1 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2009,56(7):1313-1325
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An Sang Hou 《Circuits, Systems, and Signal Processing》2005,24(1):83-101
In this paper, analog multiplexers, a threshold voltage measurement block, 16-bit analog-to-digital converter, and a computer
are employed to achieve a new scheme of threshold voltage measurement for a floating-gate MOS transistor (FGT). Feedback technology
is applied so that the threshold voltage can be measured with good accuracy. A threshold voltage measurement with a maximum
error equal to 1% can be achieved. The proposed scheme does not require any matched components, and thus it can be applied
effectively to threshold voltage measurement for multiple FGTs. The sampling time of the threshold voltage measurement is
3 ms. Dynamic responses and static characteristics are demonstrated with experimental results. 相似文献
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Described are the fundamental design principles for binary-logic circuits using a highly functional device called the neuron MOS transistor (νMOS), a single MOS transistor simulating the function of biological neurons. To facilitate logic design employing this transistor, a graphical technique called the floating-gate potential diagram has been developed. It is shown that any Boolean functions can be generated using a common circuit configuration of two-stage νMOS inverters. One of the most striking features of νMOS binary-logic application is the realization of a so-called soft hardware logic circuit. The circuit can be made to represent any logic function (AND, OR, NAND, NOR, exclusive-NOR, exclusive-OR, etc.) by adjusting external control signals without any modifications in its hardware configuration. The circuit allows real-time reconfigurable systems to be built. Test circuits were fabricated by a double-polysilicon CMOS process and their operation was experimentally verified 相似文献
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《Electron Devices, IEEE Transactions on》1979,26(11):1754-1759
A new electrically eraseable nonvolatile charge storage device is described. The electrically eraseable floating-gate avalanche injection MOS (E2FAMOS) structure is an n-channel dual-stacked-gate MOS transistor programmed by avalanche injection from the pinchoff region and erased by hot electron injection from the floating gate. 相似文献