A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture

A time-interleaved ADC architecture that eliminates the need to correct timing offsets and is yet scalable to high sampling rates is presented. To eliminate timing skews, a Nyquist rate sampling switch is used, which is followed by subsampled, double-sampled time-interleaved sample-and-hold (S/H) stages. This circuit is configured with a special clocking scheme that reduces the loading of the interleaved S/Hs on the Nyquist rate sampling switch, making this scalable to high sampling rates. The subsampled ADCs (sub-ADCs) in this design use a 3.5-bit/stage pipelined architecture. This 1-GS/s 11-bit ADC achieves 55-dB peak SNDR, 58.6-dB SNR, consumes 250-mW core power, and occupies a core area of 3.5 mm². This circuit is implemented in a dual-gate 1.2 V/2.5 V, 0.13-mum logic CMOS process     

一种带二进制校正的10位100 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种带二进制校正的10位100 MS/s逐次逼近型模数转换器(SAR ADC),主要由自举开关、低噪声动态比较器、电容型数模转换器(C-DAC)、异步SAR逻辑以及数字纠错电路组成。电容型数模转换器采用带2位补偿电容的拆分单调电容转换方案,通过增加2位补偿电容,克服了电容型数模转换器在短时间内建立不稳定和动态比较器失调电压大的问题,使SAR ADC的性能更加稳定。数字纠错电路将每次转换输出的12位冗余码转换成10位的二进制码。使用Spectre进行前仿真验证,使用Virtuoso进行版图设计,后仿真结果表明,当电源电压为1.2 V、采样率为100 MS/s、输入信号为49.903 MHz时,该ADC的SNDR达到58.1 dB,而功耗仅为1.3 mW。     

A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm², where the active area of the transmitter block is 0.5×1.2 mm².     

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100 MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100 MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57 dB at 2 MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full-scale input signal at 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.     

一个13位8兆采样率流水线模数转换器

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-andhold amplifier （SHA） is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers （opamps） are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm 1P6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW （including I/O drivers） when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm^2, including I/O pads.     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

一种用于14位250 MS/s ADC的3.5 Gb/s发送器

提出了一种用于14位250 MS/s ADC的数据发送器。该发送器输出采用电流模驱动方式,最高数据传输速率达3.5 Gb/s,数据输出仅需要2个数据端口。电路采用180 nm 1.8 V 1P5M CMOS工艺实现。测试结果表明,该发送器在3.5 Gb/s速率下的输出信号摆幅为800 mV,抖动峰峰值为100 ps,功耗为32 mW。采用该3.5 Gb/s数据发送器的ADC在250 MHz采样率下得到的信噪比为71.1 dBFS,无杂散动态范围为77.6 dB。     

A 13-bit, 8 MSample/s pipeline A/D converter

A 13-bit 8 MSample/s high-accuracy CMOS pipeline ADC is proposed. At the input, the sample-and-hold amplifier (SHA) is removed for low power and low noise; meanwhile, an improved sampling circuit is adopted to alleviate the clock skew effect. On-chip bias current is programmable to achieve low power dissipation at different sampling rates. Particularly, drain-to-source voltages in the operational amplifiers (opamps) are fixed to ensure high DC gain within the variant range of the bias current. Both on-chip and off-chip decoupling capacitors are used in the voltage reference circuit in consideration of low power and stability. The proposed ADC was implemented in 0.18-μm IP6M CMOS technology. With a 2.4-MHz input, the measured peak SNDR and SFDR are 74.4 and 91.6 dB at 2.5 MSample/s, 74.3 and 85.4 dB at 8.0 MSample/s. It consumes 8.1, 21.6, 29.7, and 56.7 mW (including I/O drivers) when operating at 1.5, 2.5, 5.0, and 8.0 MSample/s with 2.7 V power supply, respectively. The chip occupies 3.2 mm2, including I/O pads.     

A 1.2 V 10-bit 5MS/s low power CMOS cyclic ADC based on double-sampling technique

This paper presents a 1.2 V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC). The strategy to minimize the power adopts the double-sampling technique. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch is used to achieve rail-to-rail signal swing at low-voltage power supply. The prototype ADC, fabricated in TSMC 0.18 μm CMOS 1P6 M process, achieves DNL and INL of 0.32LSB and 0.45LSB respectively, while SFDR is 69.1 dB and SNDR is 58.6 dB at an input frequency of 600 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 1.68 mW.     

一种折叠内插式高速模数转换器的设计

描述了一种8bit,125MS/s采样率的折叠内插式ADC采用折叠内插结构设计。系统采用全并行结构的粗量化器实现高3位的量化编码,细量化部分采用折叠内插结构实现低5位的量化编码。电路设计中涉及分布式采样保持电路、折叠内插电路并在文章最后提出一种粗量化修正电路设计。通过HSPICE仿真测试,在采样频率为125MHz下对100M以内的输入频率测试,ADC信噪比达到40.0dB以上,功耗仅为170mW。     

A 50-MS/s (35 mW) to 1-kS/s (15 /spl mu/W) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

A novel rapid power-on operational amplifier and a current modulation technique are used in a 10-bit 1.5-bit/stage pipelined ADC in 0.18-/spl mu/m CMOS to realize power scalability between 1 kS/s (15 /spl mu/W) and 50 MS/s (35 mW), while maintaining an SNDR of 54-56 dB for all sampling rates. The current modulated power scaling (CMPS) technique is shown to enhance the power scaleable range of current scaling by 50 times, allowing ADC power to be varied by a factor of 2500 while only varying bias currents by a factor of 50. Furthermore, the nominal power is reduced by 20%-30% by completely powering off the rapid power-on opamps during the sampling phase in the pipeline's sample-and-holds.     

A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter

A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of the pipelined ADC. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. Employing double sampling and bias current scaling techniques, very competitive power consumption can be achieved. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.     

A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS

In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using this method, the ADC power consumption is reduced while improving the accuracy. The necessary current control block is shared between consecutive stages further reducing the power consumption and die area. The proposed technique is applied to a 10-bit 100 MS/s pipeline ADC designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results using Cadence Spectre show a signal-to-noise and distortion ratio of 55.6 dB with 3.56 mW power consumption resulting in a figure of merit of 72.3 fJ/conv.step without employing any calibration technique.     

Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s. The ADC’s specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels, a twice sampling front end is used. An improved averaging termination technique using intended asymmetric spatial filter response is proposed. This circuit is designed in a 0.13 μm CMOS technology with 1.2 V power supply. Simulation results show a 26 dB SNDR at 2.112 GHz sampling rate with 36 mW power consumption and the effective figure of merit value is 0.24 pJ/step.     

A 360 fJ/conversion-step, 14-bit, 100 MS/s,digitally background calibrated pipelined ADC in 130-nm CMOS

This paper describes a 14-bit digitally background calibrated pipeline analog-to-digital converter (ADC) implemented in a mainstream 130-nm CMOS technology. The proposed calibration technique linearizes the digital output to correct for errors resulting from capacitor mismatch, finite amplifier gain, voltage reference errors and differential offsets. The software-based calibration technique requires quite modest digital resources and its estimated dynamic power is under 1 % of the ADC power consumption. After calibration, the 14-bit ADC achieves a measured peak Signal-to-Noise-plus-Distortion-Ratio of 71.1 dB at 100 MS/s sampling rate. The worst-case integral nonlinearity is improved from 32.9 down to 4 Least-Significant-Bits after calibration. The chip occupies an active area of 1.25 mm² and the core ADC (S/H+analog+digital power) consumes 105 mW. The Figure-of-Merit is 360 fJ per conversion-step.     

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35$muhbox m$BiCMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier (i.e., “SHA-less”). It also has a sampling buffer that is turned off during the hold clock phases to save power. To accurately estimate and minimize the clock jitter, a new jitter simulation technique was used whose results were verified on silicon. The measured silicon results indicate the highest published IF sampling performance to date and prove the viability of the “SHA-less” architecture for IF/RF sampling ADCs. The ADC is calibration-free and achieves a DNL of less than 0.2 LSB and INL of 0.8 LSB. The SNR is 75 dB below Nyquist, and stays above 71 dB up to 500 MHz. The low-frequency SFDR is about 100 dB, and stays above 90 dB up to about 300 MHz. This is also the first ADC to achieve 14-bit level performance for input signal frequencies up to 500 MHz and to have a total RMS jitter of only 50 fs.     

A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing

A 10-MS/s-to-100-kS/s power-scalable fully differential comparator-based switched-capacitor (CBSC) 10-bit pipelined analog-to-digital converter (ADC) is presented. To operate over a wide range of sampling rates, an adaptive biasing technique is proposed to enhance both linearity and signal-to-noise-plusdistortion ratio (SNDR) at low sampling rates. This ADC has been fabricated in a 0.18-$muhbox{m}$ standard CMOS process. It achieves 62.3-dB spurious-free-dynamic range (SFDR) and 53.3-dB SNDR while being sampled at 10 MS/s and consuming 1.95 mW from a 1.8-V power supply, which obtains a figure of merit of 510 fJ/step. With the utilization of adaptive biasing, the SNDR increases from 53.3 to 56.4 dB at most when decreasing the sampling rate. In addition, its power consumption continuously reduces from 1.95 mW (10 MS/s) to 158.4 $muhbox{W}$ (100 kS/s).      

A 1 Gsps and 840 µW fully dynamic asynchronous pipelined binary search ADC

In this paper a very low power asynchronous 5-bit ADC in CMOS 45 nm process technology is described which combines the pipeline and binary search architectures. Due to utilization of dynamic non-linear amplifier, power consumption of the converter is very low. The ADC circuit uses digital calibration technique to update the reference voltages of the comparators. The power consumption of ADC is 840 µW, and the ENOB is 4.05 at 1 Gsps with input signal at the Nyquist rate. At sampling rate of 10 0Msps, the power consumption is reduced to 89 µW and the ENOB is equal to 4.6 again at the Nyquist rate.     

A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-/spl mu/m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm/sup 2/.     

A low-power multirate differential PSK receiver for space applications

Wireless communication for deep-space and satellite applications needs to accommodate the Doppler shift caused by the movement of the space vehicle and should consume low power to conserve the onboard power. A low-power phase-shift keying (PSK) receiver has been designed for such applications. The receiver employs double differential detection to be robust against Doppler shift and uses subsampling with a 1-bit A/D converter and digital decimation architecture at the front end to achieve low-power consumption. The receiver is also designed to be programmable to operate using single-stage differential detection instead of double-stage differential detection at low Doppler rates to obtain optimum performance. Furthermore, the baseband can be employed in either direct subsampling or intermediate frequency (IF)-sampling front ends. Both front ends offer minimal power consumption and differ from traditional types by replacing some conventional analog components such as a voltage-controlled oscillator, mixer, or phase-locked loop with their digital counterparts. This eliminates problems due to dc offset, dc voltage drifts, and low-frequency (LF) noise. The paper also includes a brief discussion of the nonidealities existing in real applications. The proposed phase shift keying (PSK) receiver supports a wide range of data rates from 0.1-100 Kbps and has been implemented in a CMOS process.