Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver

This letter presents a 5.7 GHz 0.18 /spl mu/m CMOS gain-controlled differential LNA for an IEEE 802.11a WLAN application. The differential LNA, fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process, uses a current-reuse technology to increase linear gain and save power consumption. The circuit measurement is performed using an FR-4 PCB test fixture. The LNA exhibits a noise figure of 3.7 dB, linear gain of 12.5 dB, P/sub 1dB/ of -11 dBm, and gain tuning range of 6.9 dB. The power consumption is 14.4 mW at V/sub DD/=1.8 V.     

An ultra-low power InAs/AlSb HEMT Ka-band low-noise amplifier

The first antimonide-based compound semiconductor (ABCS) MMIC, a Ka-Band low-noise amplifier using 0.25-/spl mu/m gate length InAs/AlSb metamorphic HEMTs, has been fabricated and characterized on a 75 /spl mu/m GaAs substrate. The compact 1.1 mm/sup 2/ three-stage Ka-band LNA demonstrated an average of 2.1 dB noise-figure between 34-36 GHz with an associated gain of 22 dB. The measured dc power dissipation of the ABCS LNA was an ultra-low 1.5 mW per stage, or 4.5 mW total. This is less than one-tenth the dc power dissipation of a typical equivalent InGaAs/AlGaAs/GaAs HEMT LNA. Operation with degraded gain and noise figure at 1.1 mW total dc power dissipation is also verified. These results demonstrate the outstanding potential of ABCS HEMT technology for mobile and space-based millimeter-wave applications.     

用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

Design of UWB switched gain controlled LNA using 0.18 μm CMOS

A switched gain controlled low noise amplifier (LNA) for the 3.1- 4.8 GHz ultra-wideband system is presented. The LNA is fabricated with the 0.18 mum 1P6M standard CMOS process. Measurement of the LNA was performed using an RF probe station. In gain mode, measured results show a noise figure of 4.68-4.97 dB, gain of 12.5-13.9 dB, and input/output return loss higher than 10/8.2 dB. The input IP3 (IIP3) at 4.1 GHz is 1 dBm, and consumes 14.6 mW of power. In bypass mode, measured results show a gain of-7.0 to -8.7 dB, and input/output return loss higher than 10/6.3 dB. The input IP3 at 4.1 GHz is 9.2 dBm, and consumes 1 muW of power.     

A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA

A sub-1-dB noise figure HBM ESD-protected [-3 kV, 2.3 kV] low noise amplifier (LNA) has been integrated in a 0.35-μm RF CMOS process with on-chip inductors. The sensitivity of the LNA performances to the spread of parasitics associated with package and bondwire has been attenuated by using an inductive on-chip source degeneration. At 920 MHz and P_dc=8.6 mW, the LNA features: noise figure NF=1 dB, input return loss=-8.5 dB, output return loss=-27 dB, power gain G _p=13 dB, input IIP3=-1.5 dBm. At a power dissipation of 5 mW and 17.6 mW, a NF respectively equal to 1.2 dB and 0.85 dB is measured. The CMOS LNA takes 12 pins of a TQFP48 package, an area of 1.0×0.66 mm² (bondwire pads excluded) and it is the first HBM ESD-protected [-3 kV, 2.3 kV] CMOS LNA to break the 1-dB NF barrier     

Low-power and low NF V-band down-converter in 0.13 μm CMOS

A V-band down-converter integrating a LNA and mixer in 0.13 mm CMOS technology is presented. The LNA has a current re-use topology for low power consumption. The transistor size of the LNA is optimised by the substrate noise for the low noise figure (NF) and f_max for high gain performance. The new resistive mixer for low LO power operation is proposed. The NF of the down-converter is 4.7 dB. The conversion gain and input P_1dB are 0.67 dB and 212.5 dBm, respectively. The proposed circuit, consuming only 11.6 mW, shows the lowest NF and highest linearity among V-band down-converters.     

6?10 GHz ultra-wideband CMOS LNA

A two-stage matched ultra-wideband CMOS low noise amplifier (LNA) is presented. The LNA is designed to achieve a low noise figure with high voltage gain. The LNA fabricated in a 0.13 mum CMOS process shows a 3.9 dB average noise figure with a 27 dB voltage gain in the 6-10 GHz frequency band with a power consumption of 14 mW.     

带有ESD保护,900MHz/2.4GHz Dual-Band CMOS LNA的设计

设计了一个可以同时工作在900 MHz和2.4 GHz的双频带(Dual-Band)低噪声放大器(LNA).相对于使用并行(parallel)结构LNA的双频带解决方案,同时工作(concurrent)结构的双频带LNA更能节省面积和减少功耗.此LNA在900MHz和2.4 GHz两频带同时提供窄带增益和良好匹配.该双频带LNA使用TSMC 0.25 μm 1P5M RF CMOS工艺.工作在900MHz时,电压增益、噪声系数(Noise Figure)分别是21 dB、2.9 dB;工作在2.4 GHz时,电压增益、噪声系数分别是25dB、2.8 dB,在电源电压为2.5 V时,该LNA的功耗为12.5mW,面积为1.1mm×0.9 mm.使用新颖的静电防护(ESD)结构使得在外围PAD上的保护二极管面积仅为8 μm×8 μm时,静电防护能力可达2 kV(人体模型)     

A 0.4 dB noise figure wideband low-noise amplifier using a novel InGaAs/InAlAs/InP device

In this work, the design of a novel low-noise amplifier (LNA) based on 1 μm gate-length InGaAs/InAlAs/InP pHEMT transistors is discussed. Designed for radioastronomy applications, this amplifier exploits a common-drain configuration as input stage and a common-source inductive degeneration topology as output stage. It exhibits a maximum gain of 30 dB within an input 1 dB compression point of −16 dBm. The noise figure is 0.4 dB with an input return loss greater than −10 dB and an output return loss of −12.5 dB. The LNA consumes 85 mW from a 1.5 V power supply.     

Low power LNA using the MOSFETs in moderate inversion

This paper presents an integrated complementary metal oxide semiconductor (CMOS) low power low noise amplifier (LNA) for global positioning system (GPS) receivers.To achieve low power dissipation,the MOS transistors in the proposed LNA are biased in moderate inversion region.It is implemented by SMIC 180 nm 1P6M CMOS process.The experiment results show that a gain of 12.14 dB@1.57 GHz is achieved with low noise figure (NF) of 1.62 dB.The power consumption of the circuit is 1.5 mW at supply voltage of 1.8 V.The ratio of gain to dc power consumption is 8 dB/mW.The size of the LNA is only 980μm× 720μm including the pads.     

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.     

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm².     

一种用于地面和有线接收机的宽带低噪声放大器

提出并设计了一种用于数字电视接收调谐芯片的宽带低噪声放大器.该设计采用0.35μm SiGe BiCMOS工艺,器件的主要性能为:增益等于18.8dB,增益平坦度小于1.4dB,噪声系数小于5dB,1dB压缩点为-2dBm,输入三阶交调为8dBm.在5V供电的情况下,直流功耗为120mW.     

Design of Low Power 2.4GHz CMOS Cascode LNA with Reduced Noise Figure for WSN Applications

In this paper, a narrowband cascode Low Noise Amplifier (LNA) with shunt feedback is proposed. A typical inductively degenerated cascode LNA can be treated as a Common Source-Common Gate (CS-CG) two stage LNA. The series interstage inductance is connected between CS-CG stages to increase the power gain. An additional inductance which is connected at the gate of CG stage is used to cancel out the parasitic capacitance of CG stage therefore reduces the noise figure of CG stage. The shunt feedback is used to improve the stability and input impedance matching. This configuration provides better input matching, lower noise figure, low power consumption and good reverse isolation. The proposed LNA exhibits the gain of 13 dB, input return loss of ?11 dB, noise figure of 2.2 dB and good reverse isolation of ?42.8 dB at a frequency of 2.4GHz using TSMC 0.13 μm CMOS technology. It produces gain and noise figure better than conventional cascode LNA. The proposed LNA is biased in moderate inversion region for achieving sufficient gain with low power consumption of 1.5mW at a supply voltage of 1.5V.     

A low power high gain UWB LNA in 0.18-μm CMOS

A low power high gain differential UWB low noise amplifier (LNA) operating at 3-5 GHz is presented.A common gate input stage is used for wideband input matching; capacitor cross coupling (CCC) and current reuse techniques are combined to achieve high gain under low power consumption. The prototypes fabricated in 0.18-μm CMOS achieve a peak power gain of 17.5 dB with a -3 dB bandwidth of 2.8-5 GHz, a measured minimum noise figure (NF) of 3.35 dB and -12.6 dBm input-referred compression point at 5 GHz, while drawing 4.4 mA from a 1.8 V supply. The peak power gain is 14 dB under a 4.5 mW power consumption (3 mA from a 1.5 V supply). The proposed differential LNA occupies an area of 1.01 mm~2 including test pads.     

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.     

0.18 μm CMOS射频低噪声放大器设计

基于TSMC 0.18μm RFCMOS工艺,设计了一种工作于2.4 GHz频段的低噪声放大器。电路采用Cascode结构,为整个电路提供较高的增益,然后进行了阻抗匹配和噪声系数的性能分析,最后利用ADS2009对其进行了模拟优化。最后仿真结果显示。该放大器的正向功率增益为14 d B,噪声系数小于2 d B,1 d B压缩点为-13 d Bm,功耗为7.8 m W,具有良好的综合性能指标。