共查询到19条相似文献,搜索用时 78 毫秒
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随着相关技术的发展,人们对频率合成器的设计也提出了更多的要求.基于这种认识,本文使用锁相环芯片设计并实现了一种频率合成器.而经过分析发现,该种合成器能够输出稳定的频率信号,并且噪声较低,能够满足合成器的设计要求. 相似文献
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文章介绍了一种新型实用的短波频率合成器。分析了该频率合成器的工作原理和设计注意事项,提出了具体的实施方案。 相似文献
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锁相环频率合成器在现代电子通信系统中有着广泛的应用。本文主要介绍了锁相环频率合成器的发展历程,各阶段的工作原理,并描述了一个锁相环频率合成器的应用实例。 相似文献
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本文研究了一种新型的微波频率合成器。该频率合成器将普通的锁相环技术和直接数字频率合成器有机地结合起来,只需在一般的单环频率合成器的基础上增加少量器件,就可以获得精确的频率分辨和相当低的相位噪声,性能大大优化单环频率合成器而仅略低于双环,结构却比环简单,成本也较低。 相似文献
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提出了一种新颖的直接频率合成器方案,实现了优于3μs的捷变频指标.采用直接数字频率合成器(DDS)实现细步进跳频,通过切换混频本振、分段开关滤波、直接倍频方式拓展输出带宽.分析了关键指标和技术难点,给出了解决措施.该频率合成器实测结果满足指标要求,具有工程应用价值. 相似文献
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低相噪数字锁相频率合成器 总被引:1,自引:1,他引:0
常规的数字锁相频率合成器具有电路简单,工作稳定可靠等特点,但由于鉴相器的倍增噪声往往比基准源的倍增噪声还要高,因而输出相位噪声较高,不能令人满意。本文提出一种双回路反馈锁相频率合成方案,成功地解决了这个问题,由于有效地抑制了鉴相器的倍增噪声,可获得较低的输出相位噪声。这种方案适用于诸如雷达系统等对频率源相位噪声有较高要求的电子设备。 相似文献
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Xiaojian Mao Huazhong Yang Hui Wang 《Analog Integrated Circuits and Signal Processing》2006,48(3):223-229
Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta
fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed
in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows
that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch
in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band
phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical
topologies of sigma-delta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design.
Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the in-band phase
noise reduction of the sigma-delta frequency synthesizer.
Xiaojian Mao was born in Jiangsu Province, China, in 1978. He received the B.S. degree in electronic engineering from Jilin University,
Changchun, China, in 2000. He is currently pursuing the Ph.D. degree in circuits and systems at Department of Electronic Engineering
of Tsinghua University, Beijing, China. His current research includes frequency synthesizers and phase-locking and clock recovery
for high-speed data communications. And His PhD thesis title is “Design and Analysis of Sigma-Delta Fractional-N PLL Frequency
Synthesizer.”
Huazhong Yang received BS, MS, and PhD Degrees in electronics engineering from Tsinghua University, Beijing, in 1989, 1993, and 1998, respectively.
He is a Professor and Head of the Circuits and Systems Division in the Department of Electronic Engineering at Tsinghua University,
Beijing. His research interests include CMOS radio-frequency integrated circuits, VLSI system structure for digital communications
and media processing, low-voltage and low-power circuits, and computer-aided design methodologies for system integration.
He has authored and co-authored 6 books and more than 100 journals and conference papers. He was the winner of Chinas National
Palmary Young Researcher Award in 2000.
Hui Wang received the B.S. degree from Department of Radio Electronics, from Tsinghua University, Beijing, China. She was a visiting
scholar at Stanford University, CA, USA from February 1991 to September 1992. Currently she is a Professor of the Circuits
and Systems Division in the Department of Electronic Engineering and the deputy dean of academic affairs office at Tsinghua
University, Beijing, China. Her research interests include modeling and simulation of radio-frequency CMOS integrated circuits,
automatic design methodology for low voltage and low-power integrated circuits, and interconnect modeling and synthesis for
deep submicron system-on-a-chip. She has authored and co-authored 4 books and over 70 papers. She was a primary research of
TADS-C4 which gained a third-grade prize for the national progress in science and technology in China in 1993. 相似文献
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介绍了一种新型的高性能雷达频率综合器的制作方法,即采用声表面波技术制作高性能的雷达频综器。采用这种方法成功地制造了L波段、S波段、C波段超低相位噪声超高速频率综合器。该类频综输出信号具有极低相位噪声(1.6GHz处:单边带相位噪声Lm(1kHz)=-127dBc/Hz;3.4GHz处:Lm(1kHz=-122dBc/Hz;6.8GHz处:Lm(1kHz)=-116dBc(Hz)、极短的频率切换时间(约160ns)、低杂波电平(L波段为-70dB;S波段为-65dB;C波段为-60dB)、较多频点(51点)等多项优异性能。同时,该频综通过了各项环境试验的考核,且长期工作性能稳定。 相似文献
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讨论了锁相式频率合成器的基本原理,设计了一种通用可编程锁相式频率合成器,介绍了其编程置型格式,提出了一种可提高程控分频器工作频率的电路设计方法,并给出了其模拟波形。该电路的最高合成频率为100MHz最小频率间隔为100Hz,在工程上具有广泛的应用前景。 相似文献