基于Verilog的有限状态机设计与优化

研究了不同的状态机编码(二进制、格雷码、独热码)和不同的状态机描述方式(one always,two always,three always)的优点和缺点,并分析了他们对有限状态机性能的影响.分别使用Xilinx ISE和Design Compiler对一个实例进行了综合,分析了其面积、速度和功耗的信息.结果表明,one always的写法需要被摒弃;two always的编码风格适合Moore型状态机;而three always的编码风格适合Mealy型状态机.同时也给出了适合不同设计的最优状态编码.     

制作简单的有限状态机

也许人们在某些教科书中见过“有限状态机”(FSM)的框图,但很可能没有人把它用于实际场合(图1).对于少数不熟悉FSM的人来说,FSM可以假设成是一个有限状态数的装丘.它的每一个状态都包含FSM某一特定条件的完整描述.FSM只能根据状态机所处状态以及输入从状态转移到状态.简单的FSM用EPROM构成,而     

卫星激光通信快速反射镜研究进展及发展趋势

快速反射镜（FSM）具有响应快、精度高、分辨率高等优势，被广泛应用于卫星激光通信、激光武器、自适应光学成像、高精度激光瞄准等领域，是捕获、跟踪和瞄准（ATP）系统中的核心部件。本文介绍了ATP系统和FSM的工作原理，并从驱动方式、FSM的面形、工作带宽、扫描角度范围、控制精度、体积重量及功耗等性能指标及在卫星激光通信的应用等方面，详细介绍了国内外研究机构的多款FSM器件，从音圈电机、压电陶瓷和微机电系统（MEMS）三种驱动结构上对FSM进行了分类，并阐述了不同驱动结构FSM的工作方式及性能差异，分析了影响FSM在ATP系统中应用的关键参数，展望了FSM在激光通信中的关键技术，指出了高精度、数字化、小型化是FSM的发展趋势。     

基于VHDL的有限状态机的优化设计

用硬件描述语言设计有限状态机在工程实际中有着广泛的应用。章分析了FSM的输出毛刺、编码原则和非法状态的处理方法，同时提出了优化方法。     

基于SPW-FSM Editor的CPM调制器的建模

CPM调制是一种非线性有记忆调制方式,其信号内在的状态转移特性更适合于用有限状态机(FSM) 来描述。SPW的FSM　Editor是一个简单易用的FSM建模工具,用其生成的FSM模型可以直接用 于SPW的BDE仿真环境中。本文给出了3RC-CPM信号的内在状态及其转移的分析,并对基于FSM Editor的建模过程进行了详细叙述,最后给出了完整的CPM调制器系统模型及其仿真波形。     

计算技术与计算机科学

Y2002-63279-94 0312747用于低功率二标准限制驱动的FSM状态编码=Two-cfiterial constraint-driven FSM state encoding for lowpower[会,英]/Koegst,M.& Rulke.S.//2001 IEEESymposium on Digital Systems Design.—94～99(TE)Y2002-63334-3231 0312748基于约束的调度=Constraint-based seheduling[会,英]/Fromherz,M.P.J.//Proceedings of the 2001 AmericanControl Conference Vol.4 of 6.—3231～3244(HE)     

低功耗UHF RFID标签基带处理器的ASIC实现

设计并实现了一种新颖的超高频RFID标签的基带处理器.该标签以ISO/IEC 18000-6C协议为基础,但在反向链路通信方面,在原协议FM0编码/Miller调制副载波的基础上增加了扩频编码的实现,目的是提高反向链路的通信信噪比.该设计支持协议要求的所有11条强制命令的读写操作,概率/分槽防冲突算法,以及对存储器的读写操作.设计中采用了低功耗技术,显著降低了芯片的平均功耗和峰值功耗.芯片采用0.18 μm6层金属CMOS工艺进行流片,面积为0.5mm2.测试结果表明,芯片消耗功耗约为16μW,最低工作电压为1.04 V.     

高通宣布Femtocell芯片组出样 产品年底上市

高通公司日前宣布Femtocell Station Modem（FSM）FSM9xxx系列芯片组已开始出样,该芯片组能够提供卓越的性能且极为易于部署。FSM产品系列支持最新的3GPP和3GPP2标准,同时通过增强的1GHz微处理器内核提供业界领先的集成度,并支持射频及功耗管理功能。首批基于FSM9xxx系列芯片组的商用产品预计将于2010年底上市。     

一种低功耗CPU卡的设计

地址总线的功耗是整个CPU卡电路系统功耗的重要来源.降低地址总线上的翻转率可以有效降低整个系统的功耗.文章在分析CMOS电路功耗和几种总线编码的基础上,提出了一种改进的T0-BI编码,并将此种编码应用于CPU卡用芯片的设计.结果表明,采用此种编码可以有效地降低CPU卡电路的功耗.     

一种二进制算术码的软解码算法

算术码是一种高效率的熵编码方法,广泛应用在多媒体压缩中.但是,算术码的高压缩性能也导致其对信道传输中残存的误码极其敏感,存在误码扩散现象.本文将算术码解码过程表示为一个有限状态机(FSM),利用最大后验概率估计准则(MAP)进行序列解码,FSM提供先验信息估计和差错检测功能.通过对独立信源和JPEG2000编码图像的实验表明,该解码算法降低了二进制算术码的序列差错率,提高了解压缩图像的质量.     

Genetic algorithm-based FSM synthesis with area-power trade-offs

Traditionally, state-encoding strategies targeting minimization of area, dynamic power or a combination of them have been utilized in finite state machine (FSM) synthesis. With drastic scaling down of devices at recent technology level, leakage power has also become an important design parameter to be considered during synthesis. A genetic algorithm-based state encoding, targeting area and power minimized FSM, has been proposed in this paper. A unified technique to reduce both static power (leakage) and dynamic power along with area trade-off has been carried out for FSM synthesis, targeting static CMOS NAND-NAND PLA, dynamic CMOS NOR-NOR PLA and pseudo-NMOS NOR-NOR PLA implementations. Suitable weights for area, leakage power and dynamic power to minimize power density have also been explored. Simulation with MCNC benchmarks shows an average improvement of 31%, 26% and 29% in leakage power consumption, dynamic power consumption and area requirement respectively, over NOVA-based state assignment technique in case of dynamic CMOS PLA implementation. Improvements of 30% in leakage power and 15% in area have been obtained for pseudo-NMOS PLA implementation. For the static CMOS case, the improvements are about 29% in leakage power consumption, 14% in dynamic power consumption and 18% in area requirement.     

Design of VHDL-based totally self-checking finite-state machine anddata-path descriptions

This paper presents a complete methodology to design a totally self-checking (TSC) sequential system based on the generic architecture of finite-state machine and data path (FSMD), such as the one deriving from VHDL specifications. The control part of the system is designed to be self-checking by adopting a state assignment providing a constant Hamming distance between each pair of binary codes. The design of the data path is based on both classical methodologies (e.g., parity, Berger code) and ad hoc strategies (e.g., multiplexer cycle) suited for the specific circuit structure. Self-checking properties and costs are evaluated on a set of benchmark FSM's and on a number of VHDL circuits     

高速倾斜镜建模与传递函数辨识

为了在光束稳定控制系统中更好地对高速倾斜镜（FSM）实现稳定、精确地控制,对于由超磁致伸缩材料（GMM）作为位移产生元件的高速倾斜镜,根据GMM 材料的特性和倾斜镜的运动机理,经推导建立了倾斜镜的传递函数模型,并结合实测的倾斜镜幅频和相频响应特性,在Matlab 软件中利用Levy 法对倾斜镜的传递函数进行了辨识,得到了精确的倾斜镜传递函数。与实测结果相比,在中低频段,幅度辨识误差在0.3 dB 以内,相位辨识误差在5以内,结果表明:通过理论推导建立的倾斜镜模型是合理有效的,对于改善该倾斜镜在应用系统中的稳定性和精度提供了依据。     

Fault identification using a finite state machine model withunreliable partially observed data sequences

The problem of minimum cost identification of a finite state machine (FSM) using a trace of its event history is addressed. The motivation is fault identification in communication systems, although other applications are possible as well. The event history used for the identification is partially observed, i.e., it is known to be a member of a regular language. Any string which belongs in this regular language is a possible trace of the FSM's event history. Furthermore, the event history is assumed to be corrupted with deletions, additions, and changes of symbols. The FSM to be estimated is related to a known FSM by performing an unknown number of additions and changes of arcs. An identification algorithm based on a fast algorithm that can correct corrupted data strings generated by a known finite state machine is developed. Examples of the method are provided, including one based on the IEEE 802.2 logical link control protocol     

Low power finite state machine synthesis using power-gating

Power-gating turns off the power supply of a portion of the circuit completely, resulting in total elimination of power consumption for that part. However, it also necessitates that the sub-circuit to be activated should be charged for some time before its activation. This critical issue can influence the decomposition of a finite state machine (FSM) for its power gated implementation. In this paper we have presented a power-gating method that integrates FSM partitioning with state encoding, thus providing a total solution to the problem of power-aware FSM synthesis. It shows better results, in terms of dynamic and leakage power consumption, compared to the existing techniques reported in the literature.     

Partitioned state encoding for low power in FPGAs

The problem of finite state machine (FSM) encoding for low power in field-programmable gate arrays (FPGAs) is addressed. In this technology, one-hot encoding is typically recommended for large FSMs and binary encoding for small FSMs. A partitioned encoding approach is proposed which uses a combination of both binary encoding and zero-one-hot encoding with intermediate code size. Experimental results demonstrate that the proposed encoding approach can produce significant power savings.     

Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory

Partitioned finite state machine (FSM) architectures in general enable low-power implementations and it has been shown that for these architectures, state memory based on both synchronous and asynchronous storage elements gives lower power consumption compared to their fully synchronous counterparts. In this paper we present state encoding techniques for a partitioned FSM architecture based on mixed synchronous/asynchronous state memory. The state memory, in this case, is composed of a synchronous local state memory and an asynchronous global state memory. The local state memory uses synchronous storage elements and is shared by all sub-FSMs. The global state memory operates asynchronously and is responsible for handling the interaction between sub-FSMs. Even though the partitioned FSM contains the asynchronous mechanism, its input/output behaviour is still cycle by cycle equivalent to the original monolithic synchronous FSM. In this paper, we discuss the low-power state encoding method for the implementation of partitioned FSM with mixed synchronous/asynchronous state memory. For the local state assignment a, what we call, state-bundling procedure is presented to enable states residing in different sub-FSMs to share the same state codes. Based on state-bundles, two state encoding techniques, in which one is the employment of binary encoding and the other is the further optimization for low power, are compared.     

基于SVM和遗传算法的变频器故障诊断研究

提出一种基于遗传算法和支持向量机的故障诊断模型.该模型采用故障识别中的分类效果作为遗传算法中的适应度函数对故障信号进行特征提取和选择,得到更能反映故障类别的特征,作为识别特征输入多类支持向量机的输入,实现不同类别故障的识别.将该模型应用于变频器功率变换主电路的故障诊断.仿真结果表明,经过遗传算法提取的特征在保持分类精度的基础上,提高了变频器故障识别的效率.     

人工神经网络与遗传算法的结合：进展及展望

近来，人工神经网络（ＡＮＮ）与遗传算法（ＧＡ）结合的研究引起了人们的极大注意。本文综述了这一领域的发展现状，并试图从两者的结合上分为辅助式及合作式两种结合方式，对于辅助式结合，ＧＡ不仅能为ＡＮＮ选择训练数据，也可用来选择网络的学习参数或学习规则，而且可利用ＧＡ解释或分析ＡＮＮ的结果；对于合作式结合，主要论述了ＧＡ作为ＡＮＮ的一种权重训练方法的不足和长处，同时评述了它与ＢＰ训练算法的优缺点，最后着重综述了利用ＧＡ自动优选ＡＮＮ的各种方法。