Modified multilevel inverter employing half- and full-bridge cells with cascade transformer and its extension to photovoltaic power generation

For the use of stand-alone photovoltaic inverters, it presents a modified multilevel inverter employing a half- and full-bridge cells with a cascade transformer. The circuit configuration is based on a prior (3ⁿ⁻¹ + 2) level inverter. Among full-bridge cells employed in the prior inverter, one cell is substituted by a half-bridge cell. Owing to this simple alteration, the proposed inverter has three promising merits. First it can increase the number of output voltage levels resulted in high quality output voltages. Second, it can reduce two power switches by means of employing a half-bridge cell. Third, it can reduce power imposed on a transformer connected with the half-bridge unit. That is to say, most power is transferred to loads via transformers connected with low switching inverters, which are used to synthesize the fundamental output voltage levels whereas the output of a transformer linked to a high switching inverter is used to improve final output voltage waves; thus, it is desirable in the viewpoint of the improvement of the system efficiency. By comparing to the prior inverter, it assesses the performance of the proposed inverter as a stand-alone photovoltaic inverter. The validity of the proposed inverter is verified by computer-aided simulations and experimental results.     

大容量多重化逆变器的输出电压谐波分析

针对目前缺乏对大容量多重化逆变器的输出电压谐波进行全面分析和比较的现状,根据多重化变压器的不同结构,将现有的典型多重化逆变器分为3类并从理论上推导出了它们的输出电压及谐波电压幅值表达式;给出了电压谐波畸变系数与重数和脉冲控制参数间的变化关系;对比分析了它们的电压谐波畸变率。理论和仿真分析结果的一致性表明由三电平逆变桥构成的多重化逆变器不仅能以较低的重数实现高压大容量输出,还可获得满意的电压谐波畸变率,且可有效减小变压器体积、重量和损耗,因而更适用于高压大容量电力电子装置。     

Cascaded Common Nodal Point Multi-level Inverter Topology

Recent trends in the multi-level inverter (MLI) technology demand reduced number of switches, driver circuits, isolated DC sources, peak inverse voltage (PIV), appreciable number of voltage level, and lower total harmonic distortion. This paper presents an improved cascaded MLI configuration. Each module comprises ten switches, two isolated DC sources, and two capacitors; it can generate a maximum of 9-level output voltage waveform. Optimized switching sequence is developed that ensures minimum switching transitions and is implemented through single-carrier pulse width modulation for the control of the proposed topology. The classical cascaded H-bridge inverter and some recently developed MLI configurations were compared with the proposed inverter circuit. Results show that the proposed inverter configuration generates high number of output voltage levels with reduced number of power switches and PIV. It also has a lower per-unit power loss profile. Unit capacitor voltage balancing scheme is developed, which ensures proper control of the unit step voltage level in each of the cascaded modules, at extreme loading condition. For two cascaded inverter modules, simulation and experimental verifications are carried out on the proposed inverter for an R–L load. Simulation results of the output voltage waveforms and its harmonic spectrum are in conformity with experimental results.     

Characteristics comparison of high‐frequency multilevel inverter connected with filter inverters

This paper presents a characteristics comparison of a high‐frequency multilevel inverter connected with small‐ capacity filter inverters. In general, PWM inverters require a low‐pass filter in order to reduce switching harmonics. However, in the high‐frequency systems such as class D power amplifiers, the cutoff frequency of the low‐pass filter must be set at high frequency. Thus, harmonic distortion of the output voltage is enlarged to a harmful level. Increasing the number of output voltage levels is effective in reducing the harmonic distortion of the output voltage and the low‐pass filter size. The proposed systems consist of a five‐level inverter and several cascade‐connected low‐voltage full bridge inverters without any external DC power sources for filtering the output voltage. The five‐level inverter generates a stepwise waveform with five‐level voltage, and the low‐voltage filter inverter superimposes harmonic components to compensate for the voltage waveform distortion. Therefore, the proposed system can reduce its total switching loss and can increase the number of the output voltage levels. In this paper, the effectiveness of the proposed systems is verified through several experiments. © 2007 Wiley Periodicals, Inc. Electr Eng Jpn, 161(3): 58–65, 2007; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20373     

死区对开环和闭环控制SPWM逆变器输出基波电压的影响

在SPWM逆变器中,为防止同一桥臂的上下两个开关器件产生直通,必须将驱动信号注入若干微秒的死区时间,这会使逆变器输出电压产生谐波电压。通过对基于瞬时输出电压反馈控制的SPWM逆变器死区效应造成的谐波电压的分析,建立了死区效应时SPWM逆变器控制模型,研究了逆变桥臂控制信号死区时间对开环与闭环控制SPWM逆变器输出基波电压的影响。分析结果表明,对于开环控制的SPWM逆变器,随着死区时间增加,逆变器输出基波电压有效值降低,输出电压谐波分量显著增加;对于单电压闭环控制的SPWM逆变器,死区时间对逆变器输出基波电压的影响与负载有关。通过仿真研究验证了理论分析的正确性。     

一种混合9电平电压源逆变器及其变频脉宽调制

介绍了一种应用于中高压变频调速装置的9电平输出电压源逆变器，逆变器的主电路由2种不同拓扑结构的逆变电路组成，分别使用不同参数的开关器件实现，可以综合利用阻断电压高的器件和开关速度快的器件的优点。分析了逆变器主电路的拓扑结构及特点，研究了主电路的开关模式后提出了一种基于载波调制的适合于任意电平数目混合逆变器的PWM(脉宽调制)算法，最后仿真研究了混合9电平逆变器在变速驱动场合中的应用，并验证了算法的有效性。对线电压的频谱分析表明，混合9电平逆变器有很好的输出波形，输出谐波含量少，在高频段输出线电压的总谐波畸变率小于5％，输出电压的dv／dt小，可用于驱动大容量的中高压异步电动机。     

基于重复控制的SPWM逆变电源死区效应补偿技术

在SPWM逆变器中,为防止同一桥臂的上下管直通现象,必须注入一定的死区时间,死区会导致逆变器的输出波形畸变,即死区效应.在分析了死区时间对单相SPWM逆变器输出波形特性的影响的基础上,提出了一种基于重复控制的死区补偿控制策略,该控制方法可有效地改善输出电压的波形畸变,并在一台单相400Hz、5.5kW装置上进行了详细的实验验证,实验结果表明了该补偿策略的有效性和实用性.     

A novel strategy for a high‐power utility interactive inverter with a series active filter

High‐power utility interactive inverters used for large‐capacity energy storage systems are composed of multiple connected inverters, in order to realize high efficiency and high performance of the harmonic elimination characteristic simultaneously. Some disadvantages of multiple connected inverters, such as harmonic current flowing from an inverter unit to the other one, and increase of the number of inverter units, cannot be overcome easily. This paper presents a novel strategy for a high‐power utility interactive inverter, which is composed of a large power with low‐switching‐frequency PWM inverter (high‐power PWM inverter), an LC passive filter, and a series active filter (series AF). Because harmonic components contained in the utility line current are absorbed by the series AF, the switching frequency of the PWM inverter can be selected to about 1 kHz. In addition because the power capacity and the output voltage of the series AF can be suppressed lower than 10% of the power capacity and the output voltage of PWM inverter, low‐voltage and high‐speed power devices can be applied to the series AF. Consequently, high power, high efficiency, and high harmonics elimination performance can be realized without increasing the number of inverter units. © 2002 Wiley Periodicals, Inc. Electr Eng Jpn, 141(2): 57–66, 2002; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10048     

Novel current‐source multilevel inverter driven by single gate drive power supply

This paper proposes a novel current‐source multilevel inverter, which is based on a current‐source half‐bridge topology. Multilevel inverters are effective for reducing harmonic distortion in the output voltage and the output current. However, the multilevel inverters require many gate drive power supplies to drive switching devices. The gate drive circuits using a bootstrap circuit and a pulse transformer can reduce the number of the gate drive power supplies, but the pulse width of the output PWM waveform is limited. Furthermore, high‐speed power switching devices are indispensable to create a high‐frequency power converter, but various problems, such as high‐frequency noise, arise due to the high dv/dt rate, especially in high‐side switching devices. The proposed current‐source multilevel inverter is composed of a common emitter topology for all switching devices. Therefore, it is possible to operate it with a single power supply for the gate drive circuit, which allows stabilizing the potential level of all the drive circuits. In this paper, the effectiveness of the proposed circuit is verified through experimental results. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 166(2): 88–95, 2009; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20475     

一种新型恒压恒频逆变电源闭环控制策略

提出一种新型三相恒压恒频（Constant-Voltage Constant-Frequence，简称CVCF）SVPWM逆变电源闭环控制策略，目的是简化控制结构并同时保持良好的控制性能。在分析两相同步旋转坐标系下逆变器输出侧数学模型的基础上。提出一种新型闭环控制策略。该方法令两相同步旋转坐标系的d轴沿输出电压矢量方向，并对输出电压d，q轴分量分别进行PI调节。利用向量图分析了所提出的控制策略的有效性。该新型闭环控制策略只需两个电压霍尔，控制结构非常简单。仿真和实验结果均证明，本文提出的闭环控制策略具有很好的稳态及动态性能。     

内蕴电压平衡控制的飞跨电容逆变器的PWM方法

采用多电平结构是逆变器实现高电压大容量化的有效途径。飞跨电容逆变器因为只需要一个独立直流供电电源、电平数易扩展、控制灵活等优点而备受青睐，但是电容电压的平衡问题却制约其推广应用。针对此问题，该文提出一种内蕴电压平衡控制的PWM方法，该方法由直接PWM算法和基于最大单元电压偏差抑制的开关状态选择法则组成，前者是由给定的ABC坐标系下的参考电压来确定逆变器所需输出的电平电压、相应的作用时间及作用顺序；后者是确定逆变器的开关状态以产生已确定的电平电压，同时控制电容电压的平衡。该PWM方法理论上适用于任意电平的飞跨电容逆变器，它不但能够有效控制电容电压的平衡，而且还能够保证功率开关频率的均衡、便于数字化实现。该文给出了该方法的数字化实现原理。最后，基于飞跨电容五电平变频器对所提出的PWM方法，做了详尽的仿真分析和大量的实验验证。     

Cascaded Multilevel Inverters Using Proposed Series Sub-multilevel Basic Blocks with Reduced Switching Devices

In this paper, a novel configuration of the cascaded multilevel inverters using series connection of new sub-multilevel basic blocks is presented. The basic structure of the proposed sub-multilevel inverter is made of three isolated batteries and eight unidirectional power switches. Hereby, by changing the polarity of one of such batteries and two power switches, two different modules of sub-multilevel inverters can be extracted that each of them is able to be incorporated into two different cascaded structures as the series basic blocks. Contemporary, to determine the suitable magnitudes of the integrated batteries, two different algorithms for each topology along with their relevant mathematical analysis have been also given. In this study, a complete comparison between the proposed topologies and several recently presented structures has been conducted. The compiled comparisons can prove the fact that both the proposed cascaded inverters are capable of generating a higher number of output voltage levels with less number of switching counts. Other advantages of these structures are reduction of voltage sources numbers, DC sources variety, value of total blocking voltage, and also conducting losses. In order to demonstrate the correct operation of the proposed structures and presented algorithms, some experimental results will be also shown.     

SIMPLE STRUCTURE MULTILEVEL INVERTER USEFUL FOR AC MOTOR DRIVES

ABSTRACT

In this paper, a new simplified configuration for a multilevel PWM inverter and its control strategy is proposed. The proposed configuration consists of an auxiliary circuit with four switching devices, and a single full-bridge inverter. For medium power applications, the new circuit design, in which the number of switching devices is reduced, offers characteristics similar to conventional NPC inverters. The control method is based on closed loop regulation of the instantaneous line-to-line output voltages. The proposed scheme is simple, has fast response, and is effective for reducing the size of the DC-link capacitors. The performance of the system is verified by computer simulation and by practical experience     

A multilevel inverter based on cascade connection of submultilevel units with reduced switch count

In this paper, a multilevel inverter based on cascade connection of new submultilevel inverters is presented. The suggested submultilevel inverter is constructed using series connection of basic switching units. The proposed multilevel inverter uses fewer power switches in comparison with some similar topologies which results in reduction of switch gate drivers and also converter size and cost. The proposed multilevel inverter can be implemented in both symmetric and asymmetric configurations. The multilevel inverter configuration and operation principle are described in detail, and then, design methods of symmetric and asymmetric configurations are given. Determination of the optimal number of basic units and cascaded submultilevel inverters regarding criteria such as number of switches and total blocking voltage (TBV) of switches is studied. Power losses of the proposed multilevel inverter are calculated, and then, its symmetric and asymmetric configurations are compared with each other and also with similar cascaded multilevel inverters in various items. The validity of the suggested cascaded multilevel inverter is verified using both computer simulations and laboratory prototype implementation.     

基于游标原理的三相逆变器算法研究

利用游标卡尺的工作原理将多个开关频率不同的逆变器串联,在每个逆变器开关频率不高的情况下得到高精度的输出波形,有效地降低了开关损耗、提高逆变器效率并延长了开关器件的寿命。最后,用仿真技术将游标原理逆变器与传统逆变器相比较：游标逆变器在开关频率仅为传统逆变器开关频率1／4的情况下输出与传统逆变器相同分辨率的电压。     

一种新型多电平逆变器在光伏并网系统的应用

传统光伏并网逆变器多采用二电平逆变器,多电平逆变器受其复杂电路拓扑的制约在光伏系统中应用较少.在传统五电平逆变器拓扑基础上,提出一种简化的H桥五电平单相光伏逆变器.该逆变器采用特定谐波消除法调制控制方案,系统并网电流采用模糊PI自整定控制方法,输出电压和电流具有较低的谐波和du/dt,改善了系统稳定性,提高了系统动态响...     

Fault-tolerant switched capacitor–based boost multilevel inverter

This paper proposes a fault-tolerant switched capacitor (SC)–based boost multilevel inverter. The proposed inverter is able to convert a low-level dc voltage into a desired ac output voltage in single-stage power conversion. It can accomplish a high voltage gain by using multiple SC cells arrangement at reduced voltage stresses on the switching devices and passive circuit elements in the boost network. The principle of operation and steady-state analysis of the proposed topology are presented to formulate the mathematical relationship between input dc and output ac voltage. In addition to that, the proposed inverter can also provide reliable electrical power supply at prescribed ac output voltage in the event of open-circuit failure of power switches. The fault tolerability is realized by reconfiguring the pulse width modulation (PWM) control scheme, whereas the reduction in output voltage is compensated by the boosting characteristic of the inverter. The effectiveness of the proposed inverter has been compared with other impedance source multilevel inverters in terms of voltage gain, boosting capability, and voltage stresses. A laboratory prototype of the proposed inverter is developed for experimentation, and its operation is validated by simulation and experimental results.     

基于阻抗匹配模式的并联逆变器均流方法

针对逆变器并联系统的动态均流问题,提出了阻抗匹配模式的逆变器并联控制方案.依据电路等效理论,将开环控制的逆变器等效为给定电压源与虚拟阻抗串联的电路形式,并给出了阻抗参数的辨识方法.以逆变器的等效电路作为被控对象模型,推导出可改变逆变器输出虚拟阻抗的控制方法.给出了并联逆变器间的虚拟阻抗匹配关系.所设计的逆变器除需共享电压给定基准正弦信号外,完全自主均流,控制方法简单.采用两台容量为1 kVA、空载输出电压为220V的逆变器并联进行了仿真和实验研究.仿真与实验结果显示:两台逆变器输出电流之差峰值小于0.1A;在负载阶跃变化中,无过渡过程.     

三相四桥臂混合五电平逆变器及其3D-SVPWM算法

混合型多电平逆变器可以用较少的开关器件输出更多的电平,常被应用于中频逆变器领域,与传统逆变器相比,具有体积小、成本低、效率高等优点。一种新型的三相四桥臂混合式五电平逆变器拓扑及其abc坐标下的SVPWM调制优化算法被提出,通过将直流端三个电容器的电压按1:2:1的比例调整,可实现输出线电压的9个电压等级。在提高了输出电平的同时,精简了电路结构,降低开关管应力。最后,通过对所提结构和3D-SVPWM算法的仿真和实验结果验证了该方法的性能。     

一种非对称结构新型多电平逆变器及其控制策略

将电力电子基本单元这一概念加以推广,提出了一种新型非对称全桥电路拓扑;详细分析了这种多电平逆变器(Multi-level Inverter,简称MLI)的工作原理和换流模式.根据新型拓扑的特点,提出了具有针对性的SHEPWM控制算法;给出了预期的波形.进一步对单相和三相逆变电路的系统进行了仿真;验证了特定谐波消除的正确性,并证明了单相m电平逆变器组合成三相后,线电压总共有2m-1个电平这一理论.