Fully integrated 2.45‐GHz OOK receiver for wireless sensor networks

This paper introduces an optimized receiver architecture using the current‐reuse technique to improve receiver sensitivity while minimizing power consumption. An ISM band wireless receiver with OOK modulation was implemented in the TSMC 0.18‐µm CMOS process. The receiver contains an RF front end, an LC‐tank based LO VCO, an IF amplifier and an OOK demodulator. In addition, the IF amplifier features a self‐mixing elimination mechanism which allows the BER to upgrade more than one order of magnitude. Measurement results show a sensitivity of ?63 dBm given a BER of 10^?3. Using the gain‐improving method, the sensitivity is improved by 4 dB (100‐kbps data rate). Including the bias circuit, overall power consumption is less than 383 μW under a 1.2‐V supply, providing an alternate solution for wireless radio applications. Copyright © 2016 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

Optical receiver front end for optically powered smart dust

The ability to create and direct beams of light means that optical communications potentially offer a large power advantage over RF communications for sensor networks. This paper presents an optically powered receiver front end for wireless optical communications. A complete optical receiver front end including a photodetector, clock and Manchester data recovery circuits has been fabricated using the UMC 180 nm CMOS process. A novel modulation scheme is described that has been devised so that this front end can recover the clock and Manchester data from an optical beam. Experimental results show that the total current consumption of the optical receiver front end is as low as 18.8 nA for a 0.5 V supply when a 1 kbps Manchester data and 8 kHz clock signal are successfully recovered. This means that photodiodes on the same substrate as the front end circuits extract enough power from the communications beam to allow the front end to work at distances of up to 10 m from the transmitter. Copyright © 2013 John Wiley & Sons, Ltd.     

A front‐end receiver with a dual cross‐coupling technique for MICS applications

This paper presents a front‐end receiver with a dual cross‐couple technique for Medical Implant Communication Services M applications, using a standard complementary metal‐oxide semiconductor process. A lower‐power design is achieved using a resistive feedback, g_m‐boosting technique along with a current reuse topology in the receiver's transconductance stage. In addition, a dual cross‐coupling configuration applied at the input stage increases overall gain performance and reduces power consumption. The measured power dissipation of the low‐noise amplifier is only 0.51 mW. The conversion gain of the receiver is 19.74 dB, while the radio frequency and local oscillator frequencies are respectively 403.5 and 393.5 MHz, and the LO power is 0 dBm. The chip exhibits excellent isolation below −70 dB from LO to intermediate frequency and LO to radio frequency. Copyright © 2016 John Wiley & Sons, Ltd.     

High‐efficiency CMOS push‐pull power amplifier with multilayer center‐tapped transformer

This paper describes the design of a push‐pull power amplifier (PA) with a center‐tapped transformer for transmitter applications on the 5.2‐GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double‐ended push–pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse‐phased cascode‐connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1‐dB compression point (P1dB), and 27.4% maximum PAE. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

In this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley & Sons, Ltd.     

Power‐efficient burst‐mode RF transmitter based on reference‐adaptive multilevel pulse‐width modulation

Burst‐mode operation of power amplifier (PA) based on multilevel pulse‐width modulation (MPWM) has been frequently discussed as a potential solution to achieve higher efficiency in radio frequency (RF) transmitters. In this paper, a novel multilevel PWM modulator is proposed that utilizes adaptive triangular reference waveforms. As compared with conventional MPWM modulators, the proposed architecture provides significant wider design space such that the efficiency of system can be effectively optimized. A general transmitter architecture based on the proposed concept is analyzed in terms of power efficiency. Efficiency optimization procedures are presented according to input magnitude statistics. Based on the proposed modulator, an optimized 2.4‐GHz RF transmitter is designed in a 0.18‐μm complementary metal‐oxide‐semiconductor (CMOS) process. The circuit‐level simulations show that it delivers 25.8‐dBm peak output power with 46.1% peak efficiency. For a 20‐MHz worldwide interoperability for microwave access (WiMAX) signal with 8.5‐dB peak‐to‐average‐power ratio (PAPR), this transmitter achieves 28.8% (average) efficiency at 17.3‐dBm (average) output power with an error vector magnitude (EVM) of 2.97% rms.     

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis,equalization, and slew rate control

A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.     

On frequency response and stability of an optical front–end with variable‐gain current amplifier using a bipolar junction transistor translinear loop

A comparative analysis of implementations of an optical front–end with variable transimpedance intended for optical storage systems in two different BiCMOS technologies is given in this article. The variable‐gain current amplifier within the optical front–end is designed by using a modified balanced type of the bipolar junction transistors translinear loop. The predictions of the optical front–end mathematical models are confirmed by the measured results. They show that a 0.6‐µm BiCMOS silicon technology implementation with worse bipolar junction transistor parameters (unity‐gain frequency, current gain β, and the Early voltage) gives much better stability than a 0.35‐µm BiCMOS silicon‐germanium technology implementation. As a consequence, the useful measured transimpedance dynamic range of the proposed optical front–end is 17.5 times larger in the 0.6‐µm BiCMOS silicon technology than that in the 0.35‐µm BiCMOS silicon‐germanium technology. Copyright © 2012 John Wiley & Sons, Ltd.     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

A 5‐Gbps USB3.0 transmitter and receiver linear equalizer

A USB3.0 compatible transmitter and the linear equalizer of the corresponding receiver are presented in this paper. The architecture and circuit design techniques used to meet the strict requirements of the overall link design are explored. Output voltage amplitude and de‐emphasis levels are programmable, whereas the output impedance is calibrated to 50Ω. A programmable receiver equalizer is also presented with its main purpose being to compensate for the channel losses; this is employed together with a DC offset compensation scheme. The 6.25‐GHz equalizer provides a 10 dB overall gain equalization and 5.5‐dB peaking at the maximum gain setting. Designed using a mature and well established 65 nm complementary metal oxide semiconductor process, the layout area is 400 µm × 210 µm for the transmitter core, and 140 µm × 70 µm for the equalizer core. The power consumption is 55 and 4 mW, respectively, from a 1.2 V supply at a data rate of 5 Gbps. The target application for such high‐speed blocks is to implement the critical part of the physical layer that defines the signaling technology of SuperSpeed USB3 PHY. However, identical iterations of the circuitry discussed can be used for similar high‐speed applications like the PCI express (PCIe). Copyright © 2014 John Wiley & Sons, Ltd.     

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley & Sons, Ltd.     

A 1–6 GHz analog radio frequency power driver in 90 nm complementary metal‐oxide semiconductor technology for wireless applications

One of the most challenging subsystems for integrated radio frequency (RF) complementary metal‐oxide semiconductor (CMOS) solutions is the power amplifier. A 1–6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on‐chip RF signal chain components at ?12 dBm power levels and produces a 0 dBm signal to on‐chip or off‐chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi‐fingered transistors. The RF driver was fabricated as a stand‐alone sub‐circuit on a 90 nm CMOS die with other sub‐circuits. Experimental tests confirmed that the on‐chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third‐order intercept point (IIP3) were ?4.7 dBm and ?0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net‐lists. Copyright © 2013 John Wiley & Sons, Ltd.     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

射频功率测量技术及其应用

功率是表征射频信号特性的一个重要参数。近年来随着移动通信技术的迅速发展,准确测量通信系统中发射机与接收机的功率已成为关键技术之一。本文首先介绍利用二极管、等效热功耗、真有效值／直流转换器及对数放大器检测射频功率的4种方法,然后阐述射频功率测量系统的优化设计。所介绍的方法均具有实用价值。     

A 60‐GHz power amplifier design with on‐chip tunable load‐matching network and power detect in 90‐nm CMOS

This paper presents a 60‐GHz power amplifier with on‐chip varactor‐based tunable load‐matching networks and an embedded DC temperature‐sensor‐based power detector. The output power can be monitored by the DC temperature sensor, and load‐matching network can be tuned by regulating the control voltage of the varactors, which can be used for correcting unpredictable process, supply voltage, and temperature (PVT) variations and load mismatch. Measured results show that the small‐signal gain of the CMOS power amplifier is up to 6.5 dB at 52 GHz. The power amplifier achieves 5 dBm output P1dB and 7 dBm saturated output power with 4.5% maximun power added efficiency (PAE) at 1 V control voltage. By sweeping the control voltage of the varactors, the power amplifier can obtain the maximun power gain, which can be used to solve the load mismatch. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

A 5‐Gbps low‐power low‐jitter voltage‐mode transmitter with two‐tap pre‐emphasis and impedance calibration in 65‐nm CMOS

A low‐power low‐jitter voltage‐mode (VM) transmitter with two‐tap pre‐emphasis and impedance calibration for high‐speed serial links is presented. Based on a comprehensive analysis of the relationship between impedance, supply current, and pre‐emphasis of the output driver, an impedance control circuit (ICU) is presented to maintain the 50 Ω output impedance and suppress the reflection, a self‐biased regulator is proposed to regulate the power supply, and an edge driver is introduced to speed up the signal transition time. Therefore, the signal integrity (SI) of the transmitter is improved with low power consumption. The whole transmitter is implemented in 65‐nm CMOS technology. It provides an eye height greater than 688 mV at the far end with a root‐mean‐squared jitter of less than 6.99 ps at 5 Gbps. The transmitter consumes 15.2 mA and occupies only 370 μm × 230 μm. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Active‐terminated transmitter and receiver circuits for high‐speed low‐swing duobinary signaling

In this work, we propose transmitter and receiver circuits for high‐speed, low‐swing duobinary signaling over active‐terminated chip‐to‐chip interconnect. In active‐termination scheme port impedance of transmitter and receiver is matched with characteristic impedance of the interconnect. Elimination of the passive terminators helps in reducing the transmitted signal level without degrading the 0signal detectability of the receiver. High‐speed current‐mode receiver and transmitter circuits are designed, so that the input port impedance of the receiver and the output port impedance of the transmitter are matched with characteristic impedance of the link. These Tx–Rx pair is used to validate the proposed active‐termination scheme. We also propose a duobinary precoder architecture suitable for high‐speed operation and a low‐power broadband equalizer topology for compensating the lossy long interconnect. The duobinary transmitter and receiver circuits are implemented in 1.8 V, 0.18 µm Digital CMOS technology. The designed high‐speed duobinary Tx/Rx circuits work up to 8 Gb/s speed while transmitting the data over 29.5 in. FR4 PCB trace for a targeted bit error rate (BER) of 10^?15. The power consumed in the transmitter and receiver circuits is 42.9 mW at 8 Gb/s. Copyright © 2010 John Wiley & Sons, Ltd.