基于VRML和Java的物理建模方法与实现

本文给出了一种基于ＶＲＭＬ和Ｊａｖａ的虚拟现实构建方法,即采用ＶＲＭＬ描述虚拟物体的几何和物理特征,用Ｊａｖａ实现物理特性,然后利用ＶＲＭＬ的Ｓｃｒｉｐｔ和ＥＡＩ将它们有机地集成在一起。为提高虚拟环境的运行度,我们提出了并实现了一种动态绘制加速为方法。     

新型体系结构概念—虚拟寄存器与并行的指令处理部件

随着程序对地址空间的需求日益提高，研究者提出了虚拟存储器概念，使程序访问的地址空间免受物理存储器的限制。随着面向寄存器的ＲＩＳＣ技术发展以及多发射结构中指令调度的日益重要，我们提出了虚拟寄存器的新概念，使寄存器空间不受物理寄存器堆大小的束缚，有利于指令调度和寄存器重新命名技术，提高指令级并行性ＩＬＰ。此外，现代新型ＲＩＳＣ处理机都着重于加强数据处理部件中的执行并行度，忽略了放在存储器中指令的处理。     

虚拟寄存器结构

虚拟存会器概念在名已经沿用近３０年，鉴于面向寄存器的ＲＩＳＣ结构的迅速发展以及寄存器对指令级并行性的重要性，本文首先提出了虚拟寄存器的新概念。虚拟寄存器结构是指令级并行调度和发射Ｔｒａｃｅ Ｍｅｒｇｉｎｇ算法在处理机体系结构上的一种实现方法。     

第二代WEB中的VRML实现技术研究

本文论述了虚拟现实、虚拟现实技术及基于ＶＲＭＬ的虚拟现实技术的概况,探讨了在第二代Ｗｅｂ上的ＶＲＭＬ虚拟境界的生成技术,提出了在ＭＶＲＣ系统中用Ｊａｖａ Ａｐｐｌｐｅｔ借助ＶＲＭＬ的外部程序接口ＥＡＩ访问ＶＲＭＬ虚拟境界及人－机交互地生成ＶＲＭＬ虚拟空间的方法,最后给出了ＶＲＭＬ的使用与开发条件。     

PJVM系统

ＰＪＶＭ是基于Ｉｎｔｒａｎｅｔ异构网络环境下的面向对象分布并行处理系统。作者采用Ｊａｖａ语言开发ＰＪＶＭ系统,利用Ｊａｖａ跨平台和平面对象的编程方法,通过扩充Ｊａｖａ对象库,在Ｉｎｔｒａｅｎｔ异构网络环境下实现了并行计算和分布式ＣＳＣＷ协同工作。最后讨论了进一步的研究,提出了利用智能Ａｇｅｎｔ支持多机群、多层次演化计算的分布并行处理的想法。     

提高VLIW指令级并行性的基本策略与技术

文章概述了ＶＬＩＷ体系结构特征,分析了在ＶＬＩＷ体系结构下开发指令级并行性的技术难点,针对影响 ＶＬＩＷ体系指令级并行性的因素阐述了一些基本的实现策略和实现技术。     

基于存储资源迭代重用的低成本寄存器重命名方法

针对超标量深流水线中物理寄存器资源冲突造成的流水线阻塞问题,提出了一种多指令共享同一物理寄存器资源的非阻塞指令发射方法。该方法可在物理寄存器资源冲突下继续分配物理寄存器,利用发射缓冲队列临时缓冲冲突的指令,增加发射流水级实际可分配的物理寄存器数量,释放发射窗口,提高物理寄存器使用的并行性。实验结果表明:相对于传统重命名方法,该方法可减少27.3%的物理寄存器资源实现传统方法相同的性能。     

VRML虚拟空间协同生成原型系统的研究与开发

以该文作者自行开发的ＶＲＭＬ虚拟空间协同生成原型系统为基础,提出了借助ＶＲＭＬ的外部程序接口ＥＡＩ,人－机交互地生成ＶＲＭＬ虚拟空间的方法;论述了通过采用集中式系统结构,利用ＧＣＰ／ＩＰ协议下的Ｊａｖａ Ｓｏｃｋｅｔ网络通信机制以及构造相应的网络通信数据包等方法,实现异地多个用协同工作的过程。     

Java处理器中指令合并技术的研究与实现

文中在分析Ｊａｖａ虚拟机及字节码特性基础上,研究了Ｊａｖａ处理器中的指令合并技术。对３种合并策略：２条指令的合并,３条指令的合并及４条指令的合并进行了分析比较,并分别实现了这３种合并策略。研究表明４条指令合并策略具有较高的性能／开销比。     

基于数据流图的异构VLIW DSP分簇方法

超长指令字数字信号处理器(VLIW DSP)的指令级并行性(ILP)主要通过指令分簇和软件流水来实现。在以前的研究中,指令分簇主要只考虑指令级并行性和减少簇间转移指令,对异构体系结构和某些寄存器只能分在指定簇上的情况考虑较少。提出一种基于数据流图(DFG)的异构体系结构上的分簇方法,利用指令的相关性将DFG划分为与簇数目相同个数的子图,再根据特殊寄存器对簇的要求采用启发式算法对子图进行调整,实验结果表明这种分簇方法使得负载更均衡,加速比相对于传统方法可以提高8%左右。     

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures

High-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. This paper reviews hardware and software techniques that alleviate the high register demands of aggressive scheduling heuristics on VLIW cores. From the software point of view, instruction scheduling can stretch lifetimes and reduce the register pressure. If more registers than those available in the architecture are required, some actions (such as the injection of spill code) have to be applied to reduce this pressure, at the expense of some performance degradation. From the hardware point of view, this degradation could be reduced if a high-capacity register file were included without causing a negative impact on the design of the processor (cycle time, area and power dissipation). Novel organizations for the register file based on clustering and hierarchical organization are necessary to meet the technology constraints. This paper proposes the used of a clustered organization and proposes an aggressive instruction scheduling technique that minimizes the negative effect of the limitations imposed by the register file organization.     

一种可用于嵌入式Java处理器的寄存器队列

提出了一种可用于Java处理器的改进型寄存器队列（FIFO）的设计和控制方法。通过在传统的指针移动型FIFO的基础上，改变读写指针的操作宽度，增加读出端口，增加旁路没计等方法，使得改进型寄存器队列可以适应Java语言字节指令的变长特性。该设计在一种针对嵌入式系统的Java虚拟机的硬件实现中得到应用，提高了Java处理的取指效率，片对随后的指令折叠提供了方便。     

On the Boosting of Instruction Scheduling by Renaming

Speculative execution is the execution of instructions before it is known whether these instructions should be executed. In the speculative execution for instruction level parallelism (ILP) processors, the concept of shadow register provides a hardware solution to maintain semantics of a program from the pollution of boosted instructions that are incorrectly predicted. In a recent study, Chang and Lai proposed a special register file based on shadow register, named conjugate register file (CRF), to support multilevel boosting in speculative execution. They also proposed a scheduling heuristic named frequency-driven scheduling to incorporate with CRF for execution. However, the ability of boosting is still constrained since the concept of register pair will force the results produced speculatively be stored in dedicated locations. Moreover, when the parallelism potential increases to tens through the advancement of hardware techniques, the heavy demand on register usage and the complexity of register file may well become a serious bottleneck for the exploitation of ILP.In this paper, the algorithm of frequency-driven scheduling is modified by replacing the function of hardware CRF with the technique of variable renaming during compilation. The new scheduling technique, named LESS, can exploit the parallelism efficiently with limited number of registers. Moreover, since the technique can benefit ILP without any special hardware support, it can be incorporated with any other ILP architecture without changing its instruction set architecture (ISA).Simulation results show that the performance achievable by LESS is better than other existing methods. For example, under the ILP model with an issue rate of 8, the speculative execution can achieve an increase of 34% in parallelism, as compared to 18% in CRF scheme.     

通过寄存器队列模型实现寄存器分配和指令调度

寄存器分配与指令调度是编译器优化过程中的两项重要任务．由于这两个阶段通常是独立完成的，寄存器分配往往会引入不必要的伪相关，从而影响指令调度的效率和结果，影响最终性能的提高．本文提出了寄存器队列模型，并在其基础上提出了一种结合实现寄存器分配和指令调度的算法，该算法能够在保证每条指令的执行时间最早的同时使用最少数目的寄存器．它的另外一个优点是具有线性的时间和空间复杂度，而且易于硬件实现．     

Register Saturation in Instruction Level Parallelism

The registers constraints are usually taken into account during the scheduling pass of an acyclic data dependence graph (DAG): any schedule of the instructions inside a basic block must bound the register requirement under a certain limit. In this work, we show how to handle the register pressure before the instruction scheduling of a DAG. We mathematically study an approach which consists in managing the exact upper-bound of the register need for all the valid schedules of a considered DAG, independently of the functional unit constraints. We call this computed limit the register saturation (RS) of the DAG. Its aim is to detect possible obsolete register constraints, i.e., when RS does not exceed the number of available registers. If it does, we add some serial edges to the original DAG such that the worst register need does not exceed the number of available registers. We propose an appropriate mathematical formalism for this problem. Our generic processor model takes into account superscalar, VLIW and EPIC/IA64 architectures. Our deeper analysis of the problem and our formal methods enable us to provide nearly optimal heuristics and strategies for register optimization in the face of ILP.     

Local variable access behavior of a hardware-translation based Java virtual machine

Hardware bytecode translation is a technique to improve the performance of the Java virtual machine (JVM), especially on the portable devices for which the overhead of dynamic compilation is significant. However, since the translation is done on a single bytecode basis, a naive implementation of the JVM generates frequent memory accesses for local variables which can be not only a performance bottleneck but also an obstacle for instruction folding. A solution to this problem is to add a small register file to the data path of the microprocessor which is dedicated for storing local variables. However, the effectiveness of such a local variable register file depends on the size and the local variable access behavior of the applications.In this paper, we analyze the local variable access behavior of various Java applications. In particular, we will investigate the fraction of local variable accesses that are covered by the register file of a varying size, which determines the chip area overhead and the operation speed. We also evaluate the effectiveness of the sliding register window for parameter passing in context of JVM and on-the-fly optimization of local variable to register file mapping.With two types of exceptions, a 16-entry register file achieves coverages of up to 98%. The first type of exception is represented by the SAXON XSLT processor for which the effect of cold miss is significant. Adding the sliding window feature to the register file for parameter passing turns 6.2-13.3% of total accesses from miss to hit to the register file for the SAXON with XSLTMark. The second type of exception is represented by the FFT, which accesses more than 16 local variables for most of method invocations. In this case, on-the-fly profiling is effective. The hit ratio of a 16-entry register file for the FFT is increased from 44% to 83% by an array of 8-bit counters.     

Floating accumulator architecture

Although technology advancement can pack more and more physical registers in processors, the numbers of architectural registers defined by the instruction set architectures (ISAs) remain relatively small on most modern processors. Exposing more architectural registers to compilers and programmers can improve the effectiveness of compiler optimization and the quality of code. However, increasing the number of architectural registers by simply adding extra bits to the register fields of instructions will expand the code size. Therefore, a better way of exposing more ISA registers without significantly expanding the code size is needed. This paper presents a new ISA called Floating Accumulator Architecture (FAA) that can expand the number of ISA registers without increasing the instruction length. Unlike the accumulator architecture whose accumulator is a fixed, special register, FAA dynamically chooses a register from the general-purpose register file as the accumulator. In other words, the accumulator in FAA is an alias to some register in the register file at any instruction, and the alias relation can be dynamically updated by FAA at any program points. Since the accumulator implicitly stores the result, the destination register field can be omitted from FAA instructions, resulting in a saving of 3 to 5 bits for each instruction. This new free instruction bit space can be utilized in two possible ways: doubling the number of ISA registers of modern 32-bit RISC processors or maintaining the number of ISA registers for 16-bit instructions on embedded processors. This paper presents the result of utilizing the free bit space to double the number of ISA registers from 16 to 32 on ARM processors, and experimental results show that performance can be improved by 7.6% on average for MediaBench benchmarks.