基于CPLDCortex M3的视频采集控制系统的设计

提出一种CPLD和Cortex M3相配合的视频采集控制系统的设计方法.以ARMv7中的Cortex M3作为CPLD控制芯片,使用EPM7128作为主控芯片,对视频解码芯片SAA7111A进行视频数据采集,具有适应性和灵活性.介绍一种高效率、低功耗的视频采集控制系统,详细论述了软硬件的设计和实现方案.采用VHDL语言编程的仿真结果表明了该系统在高速下的顺利运行.     

基于4DSP+FPGA架构数据处理板设计

为了满足超高性能数据处理以及低功耗、简单可编程性的应用,设计了一款基于TI TMS320C6678芯片和Xilinx公司XC5VSX95T芯片的4DSP+FPGA架构的数据处理板,同时设计了高带宽的数据输入输出接口以及相关的时钟、电源和复位电路,并通过具体的硬件电路实现。该数据处理板可广泛应用于航空设备、车载设备、恶劣条件下工作的特种设备,将有效提高设备的数据处理性能。     

一种小型化低功耗AFDX端系统的设计与实现

为满足航空电子系统对小型化、低功耗设计的要求,基于ARINC664 Part7标准和具体功能性能要求,设计实现了基于SOC芯片的AFDX端系统.搭建了测试验证平台,对AFDX端系统的功能性能指标进行了测试,测试结果表明,该AFDX端系统完全满足设计需求.     

Cortex-A8和H.264的无线视频监控系统设计

设计了一种基于Cortex-A8和H.264编码的无线视频监控系统.系统包含视频监控PC客户端、无线传输网络和视频采集端.视频采集端采用基于ARM Cortex-A8内核的SP5V210芯片作为中央处理器,并构建Linux系统对视频图像进行采集、H.264编码和无线传输,已编码压缩的图像数据通过实时传输协议RTP传输到视频监控PC客户端进行解码和显示.该系统具有组建快捷、灵活性强等特点,能够稳定地运行且满足设计要求,在安防系统和紧急救援系统中有着很好的应用前景.     

基于SoC的小型集成化视频采集处理系统研究

由于传统视频采集和处理系统很难解决小体积、低功耗与高数据带宽和处理速度之间的矛盾,同时针对智能武器装备、工业自动化生产等领域对视频采集与处理系统小型化、集成化发展需求,基于Xilinx公司高性能Zynq-7000系列SoC芯片,搭建了一种小型化、集成化、通用化视频采集处理平台系统。通过充分发挥SoC芯片集成ARM处理器软件可编程和FPGA硬件可编程优势,提出了利用HLS工具将图像预处理算法快速打包生成IP核,在FPGA中实现图像算法硬件加速的设计方法,不仅保证了视频采集和处理的实时性,而且实现了视频处理设备小型化、集成化、低功耗设计。对系统软硬件设计和各组成部分原理进行了介绍,并以Sobel边缘检测算子为实例,对系统功能和性能与传统处理方法进行了对比测试,验证了系统的有效性。     

基于PIC单片机的PON光功率计的设计

介绍了一种基于PIC单片机光功率计的设计.该光功率计不但能实现普通光功率的测量需求,并通过特殊设计的光路和电路结构来实现PON系统中对信号光功率测试的特殊要求,即要满足线路上3种光信号波长的同时测试、在线测试和1310 nm信号的突发测试功能,从而大大方便PON系统的安装、管理和维护.该功率计电源电路设计成软开关,实现了仪表的智能化控制.利用PIC16F877A外接的ADS1110 A/D转换芯片实现了A/D转换.PIC单片机低功耗的特性,使整个仪表功耗极低,符合手持式仪表的特点.     

基于多核处理器的高清内窥镜视频处理系统

设计一个基于TILE-Gx多核处理器的高清医用电子内窥镜视频处理系统。该系统支持2路1080p60高清视频输入输出,以及1路YCb Cr422格式高清视频的实时H.264编解码,利用现场可编程门阵列为高清视频数据提供输入输出接口,采用4片TILE-Gx多核处理器进行H.264编码解码运算,并使用1片TILE-Gx多核处理器完成系统控制、视频拼接和数据存储转发功能。实验结果表明,该系统的编解码性能满足医用内窥镜的高分辨率和实时性需求,图像质量达到了H.264的High Profile级别。     

一种嵌入式的实时视频采集系统

设计实现了一种智能移动机器人的前端视频采集系统,该系统采用视频解码芯片SAA7111A和灵活可配置的FPGA芯片实现了实时的视频采集,满足了机器人后续视频处理的需要.实验证明:该系统具有结构简单、可靠性高、使用灵活和性价比高等优点.     

基于电力线通信的视频监控系统终端设计

为满足家庭和实验室等局部小范围内快速搭建监控系统的需求,设计基于电力线通信(PLC)的视频监控系统终端。该终端系统的PLC模块实现数据在电力线上的传输,控制器模块采用S3C2440处理器芯片,基于Linux操作系统实现视频采集、数据压缩、网络传输、实时显示、存储等功能。实际监控结果表明,该终端成本低、监控网络搭建方便快速、功能扩展能力强。     

基于FPGA和DSP的机载高清VGA视频采集系统设计与实现

针对某新型机载视频测试需求的迫切性以及目前测试方法和设备不能满足试飞测试需求的问题,以TMS320DM6467T芯片为核心处理单元,采用FPGA和DSP设计技术,完成了机载高清VGA视频采集系统的硬件和软件设计,成功解决了该型机载视频的采集与处理,实现了对该机专用视频采集各要求项目的自动测试功能和自检功能;该视频采集系统已成功得到应用;实践表明,该系统能够满足测试需求,具有测试精度高、运行稳定、可扩展性好等特点。     

Toward low CPU usage and efficient DPDK communication in a cluster

In recent years, DPDK (Data Plane Development Kit, a data plane development tool set provided by Intel, focusing on high-performance processing of data packets in network applications), one of the high-performance packet I/O frameworks, is widely used to improve the efficiency of data transmission in the cluster. But, the busy polling used in DPDK will not only waste a lot of CPU cycles and cause certain power consumption, but also the high CPU usage will have a great impact on the performance of other applications in the host. Although some technologies, such as DVFS (dynamic voltage and frequency scaling, which is to dynamically adjust the operating frequency and voltage of the chip according to the different needs of the computing power of the application running on the chip, so as to achieve the purpose of energy saving) and LPI (low power idle, a technology that saves power by turning off the power of certain supporting circuits when the CPU core is idle), can reduce power consumption by adjusting CPU voltage and frequency, they can also cause performance degradation in other applications. Using thread sleep technology is a promising method to reduce the CPU usage and power consumption. However, it is challenging because the appropriate thread sleep duration cannot be obtained accurately. In this paper, we propose a model that finds the optimal thread sleep duration to solve the above challenges. From the model, we can balance the thread CPU usage and transmission efficiency to obtain the optimal sleep duration called the transmission performance threshold. Experiments show that the proposed models can significantly reduce the thread CPU usage. Generally, while the communication performance is slightly reduced, the CPU utilization is reduced by about 80%.

     

一款BD2/GPS双模导航芯片SoC子系统设计方案

介绍了一款北斗/GPS双模导航芯片中SoC子系统的设计方案.该子系统包括晶心公司设计的N10处理器、FPU协处理器,还包括 UART、I2C、SPI、GPIO 等基本外设.该 SoC子系统承载着软件的运行,并实现了处理器与外界的通信能力.根据上层软件的需求,该SoC子系统没有例化内存管理单元、缓存、外部中断管理单元等模块.该 SoC子系统分别例化了程序和数据SRAM,可以使处理器更快速地进行取指与访存.这些设计决策简化了该 SoC 子系统的设计,同时提高了处理器的运行速度,降低了芯片的功耗和面积.     

高精度超低功耗热量表的研发

通过建立热量表数学模型、选择热焓值法作为数据处理的算法，设计了基于MSP430微处理器的高精度热量表，并详细阐述了系统硬件中单片机MSP430、温度传感器和流量传感器的选择和应用；系统软件由六个模块组成。为了降低功耗，尽量缩短CPU的运行时间，利用MSP430的各工作模式，进行合理的切换和利用I／O口对模块供电进行控制。因此，设计出的热量表具有体积小、功耗低、精度高等特点。其支持USB通信方式，使用M-bus传送方式、并且实现了冷热设计重切换，为热量计量提供了新思路。     

基于SoC的VGA/LCD控制器设计和实现

在集成电路制造工艺进入深亚微米后，片上系统以其性能好、体积小、功耗低的优点得到广泛应用，通过片上总线将各个IP核连接起来。该文介绍了基于SoC的VGA/LCD图形控制器的设计与实现，使用AMBA规范中的AHB总线互连，采用迸发传输、分割传输、ping-pong帧切换以及FIFO时钟控制等技术在保证图像输出的同时，尽可能降低控制器的总线占用率。     

基于指示信号方式实现跨时钟域数据传输的方法

随着片上系统(SoC)技术的发展,芯片内各个模块交流频繁。异步系统因功耗低、速度提升潜力大和抗干扰能力强而备受青睐,但是异步电路设计复杂,数据的跨时钟域传输是亟需解决的问题。国际上目前最流行的方式是FIFO,但随着SoC复杂度的提升,一个系统上集成上百个模块,利用FIFO将会占用大量的资源,产生很大的功耗。通过分析异步传输的特点,提出一种使用指示信号来实现跨时钟域数据传输的方法,该方法与FIFO相比,在性能不减的情况下大大降低了功耗及其复杂度。利用Verilog对两个模块(CPU和FPGA)的跨时钟域数据传输进行设计仿真,通过Xilinx公司的Vivado硬件验证了其可行性。最后通过与FIFO方式的设计进行对比,说明该方法比FIFO具有更好的应用价值。     

Power-efficient and high-performance block I/O framework for mobile virtualization systems

A virtualized system generally suffers from low I/O performance, mainly caused by its inherent abstraction overhead and frequent CPU transitions between the guest and hypervisor modes. The recent research of polling-based I/O virtualization partly solved the problem, but excessive polling trades intensive CPU usage for higher performance. This article presents a power-efficient and high-performance block I/O framework for a virtual machine, which allows us to use it even with a limited number of CPU cores in mobile or embedded systems. Our framework monitors system status, and dynamically switches the I/O process mode between the exit and polling modes, depending on the amounts of current I/O requests and CPU utilization. It also dynamically controls the polling interval to reduce redundant polling. The highly dynamic nature of our framework leads to improvements in I/O performance with lower CPU usage as well. Our experiments showed that our framework outperformed the existing exit-based mechanisms by 10.8 % higher I/O throughput, maintaining similar CPU usage by only 3.1 % increment. In comparison to the systems solely based on the polling mechanism, ours reduced the CPU usage roughly down to 10.0 % with no or negligible performance loss.     

SoC设计中的时钟低功耗技术

针对时钟网络在SoC芯片中的作用和时钟网络自身的特点,研究并实现3种时钟低功耗技术,包括在系统级采用动态时钟管理技术动态地关断和配置芯片内各模块的时钟,在逻辑综合时基于功耗优化工具Power Compiler插入门控时钟单元,在时钟树综合时以时钟树规模为目标进行低功耗时钟树综合。在音视频解码芯片的设计中采用以上3种技术,结果表明其功耗优化效果明显。     

A novel portable iris recognition system and usability evaluation

We propose a new portable iris recognition system. Because existing portable iris systems use customized embedded processing units, they are limited in ability to expand to other applications, and they have low processing power. To overcome such problems, we propose a new portable iris recognition system consisting of a conventional ultra-mobile personal computer (UMPC), a small universal serial bus (USB) iris camera, and near-infrared (NIR) light illuminators. In general, portable iris systems produce considerable optical blurring. Although auto-focusing motor-driven lenses can be used to overcome it, they are too bulky to be used in a small-sized portable iris system. Therefore, we adopt an iris image restoration algorithm which performs at real-time speed. And by using a conventional UMPC as a processing unit, our portable iris system is more extensible than previous systems. In general, the performance of iris recognition has been mainly evaluated based on the quantitative metrics such as EER (Equal Error Rate), ROC (Receiver Operational Characteristics) curve or recognition time. We propose a new performance measuring method based on qualitative metrics. That is usability evaluation including user acceptance, convenience, satisfaction and resistance.     

A performance analysis of an object-based I/O architecture in a video server environment

In this paper, we present a performance analysis of how effective video server applications can be supported on personal computers (PCs) connected through a local area network (LAN). We considered both the standard 16-Mbit/s token ring and a 100-Mbit/s token ring, which follows closely the specifications for the Fiber Distributed Data Interface (FDDI). We examined three I/O architectures for a PC-based video server: an interrupt-driven I/O architecture, a peer-to-peer I/O architecture, and a concurrent, object-based I/O architecture that we proposed. The video server must support multiple MPEG-1 video streams at the same time to multiple clients on the LAN. We found that the network protocol layers require a lot of processing power, and that an implementation of our proposed I/O architecture, which takes advantage of the available power of the host processor to off-load I/O adapters, can deliver much better performance, and is more cost-effective, than other I/O architectures in a video server environment.     

生化分析仪的ARM-SoC控制系统设计

为满足小型全自动生化分析仪系统的多任务、高实时性以及数据运算复杂等要求,提出了一种基于ARM-双单片机系统的设计方法。该系统采用S3C2440A(ARM)为上位机、C8051F060单片机为下位机的系统架构,ARM与单片机之间采用串口通信方式。ARM负责任务分配和数据存贮,主单片机负责试剂盘的定位和数据采集,从单片机负责加样臂的旋转和样品加样,实现了多任务并行快速处理;系统采用嵌入式Linux和QT/E(QT/Embedded)开发软件。试验结果表明,系统具有运动控制实时性好、运算处理能力强和性能稳定可靠等优点,完全满足实际应用的需求。