图文互生转换的实现方法

图文互生转换(OMMAMT)，是指在军事决策过程中，实现由决策方案图转换生成决策方案文描述的文本，或由决策方案文中可标绘的内容转换生成方案图的过程。该文提出了图文互生转换的一种设计思路，及图文互生转换的实现途径与方法。     

一种基于图重写的计算机安全风险分析系统

基于项重写的安全风险分析的抽象规约模型在代数签名的基础上直接得到结果，没有提供相关攻击步骤明确描述，没有提供决策和攻击之间关系的统一视图，容易导致威胁的传播。为此，本文首先将图重写方案引入模型中，证明了引入图重写规则以后的风险分析系统仍然是终止的。然后利用图重写规则，提出了一种可以获得更优决策集合的方法，在改进的求带权二分图最小覆盖的方法的基础上，获得了一种具有相同时间复杂度和更高代价利益比的方法。整个模型高效、易于管理。     

基于扩展影响图的超视距空战辅助决策方法

利用扩展影响图的表示特性和计算特性来解决辅助决策系统中知识表示与问题求解的一致性问题.采用条件弧和决策簇扩展影响图解决其在描述非对称性、不确定性问题中的局限,并根据该扩展影响图提出了基于条件分解的求解算法.基于扩展影响图方法对系统进行分析并描述系统结构,给出了基于扩展影响图进行辅助任务分析设计的框架和系统结构.仿真结果表明了所提出方法的有效性.     

基于模糊认知图的情感Agent模型研究

人工情感是人工心理的一个主要研究内容。从研究人工情感出发,提出一种基于模糊认知图的情感Agent建模的方法。模糊认知图模型通过在传统认知图模型中引入模糊测度来量化概念间因果关系的影响程度。Agent的知识由内部组元的状态以及组元之间的关系权值进行描述,用简单数值运算代替了复杂的符号逻辑来实现Agent的智能推理和决策。通过实验表明,该模型设计简单、易于扩展、适用性好。     

基于符号零压缩二叉决策图的装配可行性判定方法

为了扩大装配序列规划的求解规模并提高求解效率,提升装配自动化水平,给出了装配体联接矩阵和干涉矩阵的零压缩二叉决策图描述,建立了基于符号零压缩二叉决策图的装配操作可行性判定方法。基于该方法,可以高效地求解出一个装配体的可行装配操作。结合实例验证了基于符号零压缩二叉决策图的装配体模型和可行装配操作判定方法的正确性和可行性。     

面向HDL描述基于路径覆盖的模拟矢量自动生成方法研究

提出和实现了一种面向HDL描述基于路径覆盖的模拟矢量自动生成方法,该方法在约束生成时只考虑控制语句的条件表达式，可有效避免生成冗余约束；利用扩展的决策图模型解决了中间信号到初始输入的传播问题和信号依赖关系问题，以及处理各种HDL描述风格的问题；采用约束逻辑编程方法解决了由位、位向量和整型变量组成的约束系统的统一处理问题,实验结果表明该方法能加快模拟矢量生成速度，提高路径覆盖率．生成的模拟矢量也能用于低层次设计验证和故障模拟，加快了设计进度,将该方法的原型系统用于一个32位微处理器核RTL级验证，发现了RTL级设计描述中的错误．     

基于SysML的无人侦察机需求描述方法研究

在装备论证与开发中,装备用户和研制设计人员间的需求描述往往难以沟通,造成研制工作的推迟和较大偏差.针对这种用户与研制方的需求交流障碍,借鉴SysML需求图建立武器装备需求描述的方法与步骤.主要分析了需求基本模型、需求导出模型、需求满足模型和需求验证模型等四类需求子模型.以无人侦察机需求为例,给出了基于SysML需求图对无人机顶层需求及其与设计参数之间的关系进行描述的方法.需求建模的结果表明,利用SysML需求图能够准确地对无人侦察机的需求进行描述,并且易于理解和操作.     

UML2．0顺序图的一种有穷自动机模型

为了在软件开发早期阶段对UML2．0顺序图模型进行分析和验证,本文给出了UML2．0顺序图的一种有穷自动机模型。首先给出了顺序图在语法和语义上的形式化描述,然后提出了一种使有穷自动机来描述每个对象在顺序图描述的场景中所参与的事件序列的方法,并将该方法扩展到带有组合片段的UML2．0顺序图,最后分析了UML2．0顺序图中的时间建模机制,设计了从UML2．0顺序图中提取时间约束的算法。以上工作为使用模型检测工具UPPAAL对顺序图模型进行进一步的分析与验证奠定了基础。     

基于有序二叉决策图的装配序列符号表示方法

通过建立装配状态的二进制编码和装配操作的布尔特征函数,给出了装配序列描述的有序二叉决策图(OBDD)方法;建立了从装配序列的与或图模型到OBDD模型的转换规则;并对装配序列表示的与或图模型和OBDD模型进行了存储效率比较.实验结果表明:OBDD方法具有较好的存储性能,可以改善复杂装配体的装配序列表示的存储效率,适合于复杂装配体的可行装配序列的描述.     

UML模型检测方法的研究

统一建模语言（UML）是设计和分析软件系统最常用的方法，如何保证UML模型满足某些特性是一个非常重要的问题，而模型检测是一种能够有效提高系统可靠性的自动化技术。研究了使用简单进程元语言解释器（SPIN）对UML模型进行检测的方法。首先对UML模型进行形式化描述，使用层次自动机来描述状态图，然后根据层次自动机的操作语义将状态图和类图的部分信息转化为SPIN的输入语言PROMELA，使用SPIN来验证模型是否满足给定的线性时序逻辑所描述的系统约束，通过LTL公式描述顺序图的方式来验证与状态图之间的一致性问题。项目组基于此方法还开发了一套模型检测工具UMLChecker。     

A knowledge-based expert system for automatic visual VLSI reverse-engineering: VLSI layout version

This paper presents a method of knowledge representation for very large scale integration (VLSI) chip design which provides the necessary information for abstraction from the physical design to gate-level logic through a high-level behavioral model. The representation scheme used by the ANTISTROFEAS system utilizes a hierarchical attributed graph structure which consists of incrementally abstracted design information for the VLSI system. This method of knowledge representation is well-suited to reverse-engineering of VLSI chips from the layer mask layout data, but is also applicable to applications at many levels of the design process including design rule checking, logic synthesis, design verification, and partitioning-compaction problems. The representation scheme is applicable to any VLSI technology, and is designed to take advantage of artificial intelligence. expert system techniques, by disassociating the representation and manipulation of the VLSI design data from the rules which govern its correctness and transformation for other usage.     

The applicability of discrete performance estimation methods to VLSI design

Conditions necessary to produce correct asymptotic complexity results and realistic performance estimates for VLSI devices, using discrete high-level VLSI complexity models, are examined. A set of design constraints is formulated, based on results from two experiments involving suitably designed and fabricated VLSI devices. The basis of the complexity model is modified so that it satisfies the constraints. A case-study for an integer multiplier design shows that the modified model produces asymptotic results in agreement with empirical measurements. Low-level performance estimates are then obtained using the RC network delay model in conjunction with the VLSI complexity model.This work was partly supported by the SERC/Alvey Programme (Project no. VLSI/ARCH 005)     

VLSI低功耗设计方法的研究

针对近年来VLSI 功耗问题越来越被关注,尤其是在电池供电的便携式设备中CMOS 电路的功耗问题尤为重 要。本文对VLSI 的低功耗设计方法进行了研究,首先对VLSI 作了简介,其次分析了VLSI 的功耗来源,最后就如何实现VLSI 开关功耗的低功耗设计,着重讨论了几项技术。本文对电子行业从业人员有一定的积极意义。     

Continuous-valued probabilistic behavior in a VLSI generative model

This paper presents the VLSI implementation of the continuous restricted Boltzmann machine (CRBM), a probabilistic generative model that is able to model continuous-valued data with a simple and hardware-amenable training algorithm. The full CRBM system consists of stochastic neurons whose continuous-valued probabilistic behavior is mediated by injected noise. Integrating on-chip training circuits, the full CRBM system provides a platform for exploring computation with continuous-valued probabilistic behavior in VLSI. The VLSI CRBM's ability both to model and to regenerate continuous-valued data distributions is examined and limitations on its performance are highlighted and discussed.     

Functional-Level Fault Simulation with Concurrent and Parallel Mechanisms Using Object-Oriented VLSI Model

The functional-level test has been proposed as an alternative to reduc the complexity of test when VLSI gets larger and more complicated.It has been successful for circuits such as memories,PLAs and microprocessors.However,the functional-level test for general functional models has sedldom been studied.This paper presents an object-oriented VLSI model and a functional-level fault simulation methodology for general functional model.Based on the proposed VLSI model,FFS(Functional-level Fault Simulator)with friendly visual interface has been implemented on Microsoft Windows platform by use of C .It is an integral part of MVS(Functional test Modeling and Verification System)--an extended subsystem of TeDS(Test Development System).The goal of FFS is to determine the fault coverage,generate fault dictionary and compact original test set at the function-level.In order to be efficient,FFS uses the concurrent and parallel mechanisms by taking advantage of the object-oriented VLSI model.The object-oriented VLSI model based fault simulation has been validated in the functional-level test by simulation results and the satisfying performance of FFS.     

单通道VLSI阵列容错的神经网络算法

为了解决大面积的VLSI（超大规模集成电路）电路制造过程中因缺陷而造成的成品率低的问题，可以采用降阶和冗余两种VLSI阵列重构方法，这两种方法都属于NP-完全问题。该文是通过冗余修复方法来解决这一问题的。该文基于Hopfield神经网络为模型，将阵列的重构问题转化为矛盾图的最大独立集问题。通过Hopfield神经网络的能量函数方程进行求解，求得合理的补偿通道来完成问题的求解。实验分析表明该方法是简单有效的。     

Representation and Reasoning Under Uncertainty in Deception Detection: A Neuro-Fuzzy Approach

An analysis of the process and human cognitive model of deception detection (DD) shows that DD is infused with uncertainty, especially in high-stake situations. There is a recent trend toward automating DD in computer-mediated communication. However, extant approaches to automatic DD overlook the importance of representation and reasoning under uncertainty in DD. They represent uncertain cues as crisp values and can only infer whether deception occurs, but not to what extent deception occurs. Based on uncertainty theories and the analyses of uncertainty in DD, we propose a model to represent cues and to reason for DD under uncertainty, and address the uncertainty due to imprecision and vagueness in DD using fuzzy sets and fuzzy logic. Neuro-fuzzy models were developed to discover knowledge for DD. The evaluation results on five data sets showed that the neuro-fuzzy method not only was a good alternative to traditional machine-learning techniques but also offered superior interpretability and reliability. Moreover, the gains of neuro-fuzzy systems over traditional systems became larger as the level of uncertainty associated with DD increased. The findings of this paper have theoretical, methodological, and practical implications to DD and fuzzy systems research.     

VLSI数据库系统的物理设计和实现技术

在VLSI芯片的设计过程中,所牵涉到的设计数据的数量是巨大的,数据库管理系统则起着十分重要和不可替代的作用。本文依据VLSI设计过程的特点和要求以及设计数据的类型与特征,研讨适用于VLSI CAD系统中的数据库管理系统的物理设计和实现问题,同时给出一个实际设计的VLSI数据库系统的数据模型和组织方式以及物理结构。     

A Tree Matching Algorithm and VLSI Architecture for Real-Time 2D Object Classification

This paper presents a real-time classification algorithm for two-dimensional (2D) object contours using a tree model which is implemented in a modular very large scale integration (VLSI) architecture. The hardware implementation takes advantage of pipelining, parallelism, and the speed of VLSI technology to perform real-time object classification. Using the multiresolution tree model, the classification algorithm is invariant under 2D similarity transformations and recognizes the visible portions of occluded objects. The VLSI classification system is implemented in 0.8 mm CMOS and is capable of performing 34 000 matchings per second.     

FP──VLSI自动综合系统

ＦＰ—ＶＬＳＩ自动综合系统是一个集成化的ＶＬＳＩ自动设计工具，它能完成从并行算法到脉动算法到脉动结构再到逻辑结构最后到ＣＭＯＳ版图的自动综合过程．ＦＰ—ＶＬＳＩ系统以脉动阵列为ＶＬＳＩ的体系结构，采用具有良好代数性质的ＦＰ／Ｂ语言作为各层次的描述语言，通过程序变换进行综合和优化．该系统支持形式化的ＶＬＳＩ设计方法，能保证设计结果的正确性．