二值触发器和三值触发器的关系

本文研究二值触发器和二值触发器的关系。当三值信号中有一值不会出现时，各型三值触发器在功能上将转化为相应类型的二值触发器，立即转化为相同结构的二值触发器，另一些三值触发器结构稍加变换也转化为常用结构的二值触发器，便于用统一的方法研究三值时序电路，以及二值与三值混合的时序电路。     

多值触发器及其在时序电路设计中的应用

本文对于多值逻辑代数系统中的基本运算和实现这些基本运算的门电路，作了必要的阐述。作者将ＤＹＬ集成线性“与或“门，用来设定多值逻辑电平的基础上，提出了多值Ｄ、Ｔ、ＪＫ等触发器电路，并将这类多值触发器，作为多值逻辑器件，用于时序电路设计。     

聚乙烯装置模块多变量在线操作指导

提出了模块多变量在线操作指导系统的一般性框架结构，并设计了一个模块多变量在线操作指导系统．它能及时给出合适的线性低密度聚乙烯反应器催化剂操作量的指导值，预防反应器温度超高限运行；在稳定反应器的温度、生产负荷和床层重量方面取得了良好效果．     

基于连续逻辑的多值同步时序电路模块设计

本文对多值时序逻辑电路提出了一种新的设计思想:以连续逻辑中不同的逻辑电平来表示时序机状态集中的不同状态及其他参数集中的不同元素;以电容及其旁路MOS管代替触发器实现信号的暂存和抹除.由于取消了传统的以一个二进制码代表一种状态的方法,使设计过程大大简化,可以使用多值时序电路的通用模块.实现不同的时序函数只需改变模块中某几个接点,所以设计、制造和使用都很方便.     

同步时序电路测试生成研究

本文分析了固定故障所反映出的状态变换特征，提出状态变换故障模型。基于无复位时序电路，详细研究了有复位的同步电路测试生成问题及在无复位电路中的应用。最后讨论了故障精简以及启发知识在测试过程中的应用。     

单链扫描可测性设计中存储元件的排序

本文提出了扫描设计中存储元件在扫描链中的最优排序方法，采用交迭测试体制和区间法能快速求出最优解，对于确定的测试向量集，用该方法的构造的扫描链能使电路总的测试时间最少。     

基于CPLD和VHDL的一种线阵CCD驱动电路的设计

本文介绍了线阵CCD的工作原理和结构,运用VHDL硬件描述语言,结合复杂可编程逻辑器件CPLD,完成了对线阵CCDT1702C的驱动时序电路的设计,给出了部分VHDL语言代码,利用QuartusII软件实现了时序仿真。     

同步时取电路优化中的时序重构技术

本文论述了８０年代初以来，同步时序电路优化方法中出现的时序重构技术的基本理论、方法和应用，并指出了此技术进一步实用化的几种方法．     

一种时序电路的测试生成算法

本文提出了一种高效的时序电路测试生成算法,该算法是建立在自适应算法的基础上,并使用了十七值逻辑模型。文章详细介绍了该测试算法的内容及其实现过程,并举例说明了该算法的测试效率。     

时序逻辑电路的Petri网分析方法

本文应用带抑止弧的增广Ｐｅｔｒｉ网，建立了基本门电路和常用触发器的Ｐｅｔｒｉ网模型，讨论了运用该模型描述同步和异步时序逻辑电路，给出了增广Ｐｅｔｒｉ网的矩阵描述和状态转移方程，在此基础上提出了同步和异步时序逻辑电路统一分析的Ｐｅｔｒｉ网方法。     

限幅电压开关理论及三值TTL电路的开关级逻辑设计

本文根据作者对CMOS电路的研究经验,在分析二值与三值TTL反相器工作过程的基础上,讨论了TTL电路中晶体管开关元件与信号之间的相互作用过程,并由此建立了适用于TTL电路的限幅电压开关理论,设计实例表明,该理论不仅可用于指导三值TTL电路的设计,而且还可用于指导二值TTL电路的设计,由此显示出该理论的实用意义。     

Toward novel designs of reversible ternary 6:2 Compressor using efficient reversible ternary full-adders

Integrated circuits always face with two major challenges including heat caused by energy losses and the area occupied. In recent years, different strategies have been presented to reduce these two major challenges. The implementations of circuits in a reversible manner as well as the use of multiple-valued logic are among the most successful strategies. Reversible circuits reduce energy loss and ultimately eliminate the problem of overheating in circuits. Preferring multiple-valued logic over binary logic can also greatly reduce area occupied of circuits. When switching from binary logic to multiple-valued logic, the dominant thought in binary logic is the basis of designing computational circuits in multiple-valued logic, and disregards the capabilities of multiple-valued logic. This can cause a minimal use of multiple-valued logic capabilities, increase complexity and delay in the multiple-valued computational circuits. In this paper, we first introduce an efficient reversible ternary half-adder. Afterward, using the reversible ternary half-adder, we introduce two reversible versions of traditional and comprehensive reversible ternary full-adders. Finally, using the introduced reversible ternary full-adders, we propose two novel designs of reversible ternary 6:2 Compressor. The results of the comparisons show that although the proposed circuits are similar to or better than previous corresponding designs in terms of criteria number of constant input and number of garbage outputs, they are superior in criterion quantum cost.

     

Quantum ternary parallel adder/subtractor with partially-look-ahead carry

Multiple-valued quantum circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum circuits. Binary parallel adder/subtractor is central to the ALU of a classical computer and its quantum counterpart is used in oracles – the most important part that is designed for quantum algorithms. Many NP-hard problems can be solved more efficiently in quantum using Grover algorithm and its modifications when an appropriate oracle is constructed. There is therefore a need to design standard logic blocks to be used in oracles – this is similar to designing standard building blocks for classical computers. In this paper, we propose quantum realization of a ternary full-adder using macro-level ternary Feynman and Toffoli gates built on the top of ion-trap realizable ternary 1-qutrit and Muthukrishnan–Stroud gates. Our realization has several advantages over the previously reported realization. Based on this realization of ternary full-adder we propose realization of a ternary parallel adder with partially-look-ahead carry. We also show the method of using the same circuit as a ternary parallel adder/subtractor.     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

Towards quantum reversible ternary coded decimal adder

Quantum ternary logic is a promising emerging technology for the future quantum computing. Ternary reversible logic circuit design has potential advantages over the binary ones like its logarithmic reduction in the number of qudits. In reversible logic all computations are done in an invertible fashion. In this paper, we propose a new quantum reversible ternary half adder with quantum cost of only 7 and a new quantum ternary full adder with a quantum cost of only 14. We termed it QTFA. Then we propose 3-qutrit parallel adders. Two different structures are suggested: with and without input carry. Next, we propose quantum ternary coded decimal (TCD) detector circuits. Two different approaches are investigated: based on invalid numbers and based on valid numbers. Finally, we propose the quantum realization of TCD adder circuits. Also here, two approaches are discussed. Overall, the proposed reversible ternary full adder is the best between its counterparts comparing the figures of merits. The proposed 3-qutrit parallel adders are compared with the existing designs and the improvements are reported. On the other hand, this paper suggested the quantum reversible TCD adder designs for the first time. All the proposed designs are realized using macro-level ternary Toffoli gates which are built on the top of the ion-trap realizable ternary 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.     

三值组合电路的冒险分析

本文首先讨论了基于函数与／或表示形式的三值组合电路中的竞争冒险现象，提出应用代数法与Ｋ图法等二种分析与消除竞争冒险的技术。其次，本文分析了另一类多值电路中所固有的冒险现象－渡越冒险，指出它们属于一种电路的正常反应，但可采用快变信号与负载电容等方法加以抑制。     

基于MODCPSO算法的三值FPRM电路面积与延时优化

针对三值固定RM(fixed polarity reed-muller,FPRM)逻辑电路面积与延时综合优化问题进行了研究,提出了一种基于竞争行为多目标离散粒子群算法(Multi-Objective Discrete Competitive Particle Swarm Optimization,MODCPSO)的极性搜索方案。首先在MODCPSO算法中,引入竞争行为机制,将种群划分为不同的团队,从各个团队中随机抽取两个粒子进行比较,令较差的粒子向着较好的粒子进行速度和位置的更新。同时引入变异机制,令种群粒子能够跳出局部最优解,继续更新进化。然后,结合三值FPRM极性转换技术和MODCPSO算法搜索电路面积与延时的最佳极性。最后,利用PLA格式的MCNC Benchmark电路实现算法测试,并与DPSO算法、MODPSO算法进行了性能对比。实验结果验证了MODCPSO算法的有效性。     

三值光计算机百位编码器的设计与构造

本文介绍一个用市售液晶显示模块构造百位量级的三值光计算机编码器的设计方案，同时介绍用图形点阵液晶显示模块YM12832A制作编码器的核心部件--编码屏的方法，以及驱动和控制该编码屏工作的电路连接和工作原理。文中还简略介绍了百住量级三值光计算机解码器的构造方案。     

CMOS Design of Ternary Arithmetic Devices

This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.     

CNFET-based approximate ternary adders for energy-efficient image processing applications

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.