Testing And Applications of Inverter-Free PLAs

The testing properties of inverter-free PLAs make them ideal for application to totally self-checking and easily testable circuits. After a class of test patterns and masking relations for these new patterns are determined, a complete test set for single and multiple crosspoint faults can be easily generated. Moreover, the procedure does not require any fault simulation. The code space inputs detect all single and multiple faults in PLAs for totally self-checking circuits, even if the faults are not unidirectional. The test results can be used to analyze easily testable PLAs. With minor hardware changes in one-input decoder PLAs, the personality matrix will serve as a complete test set.     

Agile product-line architecting in practice: A case study in smart grids

ContextSoftware Product Line Engineering implies the upfront design of a Product-Line Architecture (PLA) from which individual product applications can be engineered. The big upfront design associated with PLAs is in conflict with the current need of “being open to change”. To make the development of product-lines more flexible and adaptable to changes, several companies are adopting Agile Product Line Engineering. However, to put Agile Product Line Engineering into practice it is still necessary to make mechanisms available to assist and guide the agile construction and evolution of PLAs.ObjectiveThis paper presents the validation of a process for “the agile construction and evolution of product-line architectures”, called Agile Product-Line Architecting (APLA). The contribution of the APLA process is the integration of a set of models for describing, documenting, and tracing PLAs, as well as an algorithm for guiding the change decision-making process of PLAs. The APLA process is assessed to prove that assists Agile Product Line Engineering practitioners in the construction and evolution of PLAs.MethodValidation is performed through a case study by using both quantitative and qualitative analysis. Quantitative analysis was performed using statistics, whereas qualitative analysis was performed through interviews using constant comparison, triangulation, and supporting tools. This case study was conducted according to the guidelines of Runeson and Höst in a software factory where three projects in the domain of Smart Grids were involved.ResultsAPLA is deployed through the Flexible-PLA modeling framework. This framework supported the successful development and evolution of the PLA of a family of power metering management applications for Smart Grids.ConclusionsAPLA is a well-supported solution for the agile construction and evolution of PLAs. This case study illustrates that the proposed solution for the agile construction of PLAs is viable in an industry project on Smart Grids.     

Designing CMOS Circuits for Switch-Level Testability

Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. The circuit is implemented with specially designed gates that have no undetectable stuck-on faults. An inverting buffer is inserted between logic gates, and two FETs are added to each logic gate to make it testable for stuck-on faults.     

Smile: a computer program for partitioning of programmed logic arrays

This paper presents a new approach to optimal topological design of PLAs (programmed logic arrays). In particular we address the array partitioning problem and the implementation of partitioned arrays as block folded or parallel connected PLAs. We present a graph theoretic interpretation of the problem and an efficient heuristic algorithm. A computer program, Smile, is described and experimental results are reported.     

MCU可测性设计的实现

由于 MCU(Micro-Controller Unit)的结构非常复杂 ,因此若在设计时采用一般数字电路设计的从结构出发的 DFT(Design For Testability)技术 (包括扫描设计和 BIST—— Built-In Self-Test)将使电路的规模急剧增大。本文从功能测试的角度出发 ,提出了一种在 MCU中加入规模很小的模式选择电路 ,对部分电路作较小改动 ,就使芯片内的各块电路都可被测试的方法。在完成了 MCU 的可测性设计(Testable Design)后进行了仿真     

基于耦合测试信息元数据模型的构件集成测试

文中提出一个方法,由构件开发方提供有关构件内接口变量定义和使用的信息,以提高构件的可测试性和可理解性.形式化地定义了构件耦合测试准则,定义-使用属性和观察点值.在此基础上,引入包含上述两项属性的定义-使用表(DU表),给出基于该表的构件框架.最后将上述方法应用于自主开发的构件中,并生成了相应的测试用例.将文中提出的方法与Orso方法和Kan方法进行了相关的比较,结果表明文中方法无论在测试用例生成,还是在变异发现上都更有效.     

A Knowledge-Based System for Designing Testable VLSI Chips

The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designing more easily tested circuits have evolved over the years, with particular emphasis on built-in testing approaches. What has not evolved is a design methodology for evaluating and making choices among the numerous existing approaches. This article describes efforts to build a knowledge-based expert system for designing testable VLSI chips. A framework for a methodology incorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques is introduced. This methodology provides a designer with a systematic DFT synthesis approach. The process of partitioning a design into subcircuits for individual processing is described and a new concept?I-path?is used to transfer data from one place in the circult to another. Rules for applying testable design methodologies to circuit partitions and for evaluating the various solutions obtained are also presented. Finally, a case study using a prototype system is described.     

Recent Developments in the Theory and Practice of Testable Logic Design*

This paper surveys and summarizes the major contributions to the theory and practice of testable logic design. The first part, dealing with the theoretical procedures, discusses the design of easily testable combinational, sequential, and iterative networks, illustrating major techniques with common running examples. The second part comments on the more practical aspects such as board layout, test point siting, and other facilities for easing the problems associated with testing.     

A tutorial on built-in self-test. 2. Applications

For pt.1 see ibid., vol.10, no.1, p.73-82 (1993). The hardware structures and tools used to implement built-in self-test (BIST) pattern generation and response analysis concepts are reviewed. The authors describe testing approaches for general and structured logic, including ROMs, RAMs, and PLAs. They illustrate BIST techniques with real-world examples     

Macro Testing: Unifying IC And Board Test

Historically, IC testing and board testing have been considered two separate subjects. However, today's increasing complexity in both design and technology has given rise to a number of efforts to produce a consistent test strategy that smoothly couples both types of testing. This article describes one such effort by Philips, a design for testability methodology for semicustom VLSI circuits. The methodology is based on the partitioning of a design into testable macros, hence the term ?macro testing.? The challenges in this approach are the partitioning itself, the selection of a test technique suited to the separate macros and the chip's architecture, the execution of a macro test independent of its environment, and the assembly of macro tests into a chip test.     

SOC的可测性设计策略

通过一则设计实例研究SOC(System On Chip)的可测性设计策略;15针对系统中的特殊模块采取专用的可测性策略,如对存储器进行内建自测试,对锁相环测试其性能参数等;其它模块采用基于ATPG(Automatic Test Pattern Generation)的结构化测试方法进行测试,同时设计一些控制模块优化测试结构;经验证,应用这些策略,在满足了功耗和面积要求的前提下,系统总测试覆盖率达到了98.69%,且具有期望的可控制性和可观察性;因此在SOC设计中应灵活采用不同测试策略,合理分配测试资源从而达到预期的测试效果。     

Exploring convenience in mobile commerce: Moderating effects of gender

To date, little research has examined gender difference in how convenience is perceived in mobile commerce (m-commerce). The current work presents and tests a theoretical model partially based on Technology Acceptance Model (TAM), and posits a sequential relationship among four primary dimensions: (1) intrinsic attributes of mobile device—portability and interface design; (2) ease of use; (3) extrinsic attributes of mobile device—simultaneity, speed, and searchability; and (4) perceived convenience of m-commerce. We posit that physical attributes of mobile device (portability and interface design) are antecedents of ease of use, which in turn determines three extrinsic attributes (simultaneity, speed, and searchability). The final dependent variable is perceived convenience. Based on prior research on TAM and gender theories, the study proposes 16 hypotheses, of which our data support 12. Our results indicate that the link between interface design and ease of use holds a key to motivate females’ use of m-commerce. In closing, implications are discussed while important limitations are recognized along with future research suggestions.     

More testable properties

Testing remains a widely used validation technique for software systems. However, recent needs in software development (e.g., in terms of security concerns) may require to extend this technique to address a larger set of properties. In this article, we explore the set of testable properties within the Safety-Progress classification where testability means to establish by testing that a relation, between the tested system and the property under scrutiny, holds. We characterize testable properties w.r.t. several relations of interest. For each relation, we give a sufficient condition for a property to be testable. Then, we study and delineate a fine-grain characterization of testable properties: for each Safety-Progress class, we identify the subset of testable properties and their corresponding test oracle. Furthermore, we address automatic test generation for the proposed framework by providing a general synthesis technique that allows to obtain canonical testers for the testable properties in the Safety-Progress classification. Moreover, we show how the usual notion of quiescence can be taken into account in our general framework, and, how quiescence improves the testability results. Then, we list some existing testing approaches that could benefit from this work by addressing a wider set of properties. Finally, we propose Java-PT, a prototype Java toolbox that implements the results introduced in this article.     

Interaction semantics with refusals,divergence, and destruction

Formal methods for testing the conformance of a software system to its specification are considered. The interaction semantics determines the testing capabilities, which are reduced to the observation of actions and refusals (absence of actions). The semantics is parameterized by the families of observable and unobservable refusals. The concept of destruction as a prohibited action that should be avoided in the course of interaction is introduced. The concept of safe testing, the implementation safety hypothesis, safe conformance, and generation of a complete test suite based on the specification are defined. Equivalences of traces, specifications, safety relations, and interaction semantics are examined. A specification completion is proposed that can be used to remove from the specification irrelevant (not included in the safely testable implementations) and nonconformal specification traces is proposed. The concept of total testing that detects all the errors in the implementation (rather than at least one error as is the case in complete testing) is introduced. On the basis of the analysis of dependences between errors, a method for the minimization of test suites is proposed. The problem of preserving the conformance under composition (the monotonicity of conformance) is investigated, and a monotone transformation of the specification solving this problem is proposed.     

Components meet aspects: Assessing design stability of a software product line

Context

It is important for Product Line Architectures (PLA) to remain stable accommodating evolutionary changes of stakeholder’s requirements. Otherwise, architectural modifications may have to be propagated to products of a product line, thereby increasing maintenance costs. A key challenge is that several features are likely to exert a crosscutting impact on the PLA decomposition, thereby making it more difficult to preserve its stability in the presence of changes. Some researchers claim that the use of aspects can ameliorate instabilities caused by changes in crosscutting features. Hence, it is important to understand which aspect-oriented (AO) and non-aspect-oriented techniques better cope with PLA stability through evolution.

Objective

This paper evaluates the positive and negative change impact of component and aspect based design on PLAs. The objective of the evaluation is to assess how aspects and components promote PLA stability in the presence of various types of evolutionary change. To support a broader analysis, we also evaluate the PLA stability of a hybrid approach (i.e. combined use of aspects and components) against the isolated use of component-based, OO, and AO approaches.

Method

An quantitative and qualitative analysis of PLA stability which involved four different implementations of a PLA: (i) an OO implementation, (ii) an AO implementation, (iii) a component-based implementation, and (iv) a hybrid implementation where both components and aspects are employed. Each implementation has eight releases and they are functionally equivalent. We used conventional metrics suites for change impact and modularity to measure the architecture stability evaluation of the 4 implementations.

Results

The combination of aspects and components promotes superior PLA resilience than the other PLAs in most of the circumstances.

Conclusion

It is concluded that the combination of aspects and components supports the design of high cohesive and loosely coupled PLAs. It also contributes to improve modularity by untangling feature implementation.     

FREE模型在面向对象测试中的应用研究

在面向对象分析设计中，对象的进行为通常与其状态紧密相关。因此，基于状态的测试成为面向对象软件中一个有效的测试方法。对FREE模型进行了研究，分析了该模型的优缺点及适用范围，并将其应用于面向对象软件测试中，为基于状态的测试提供一个类行为的可测模型，有利于提高面向对象的测试质量。     

IDDT: Fundamentals and Test Generation

It is the time to explore the fundamentals of IDDT testing when extensive work has been done for IDDT testing since it was proposed.This paper precisely defines the concept of average transient current(IDDT) of CMOS digital ICs,and experimentally analyzes the feasibility of IDDT test generation at gate level.Based on the SPICE simulation results,the paper suggests a formula to calculate IDDT by means of counting only logical up-transitions,which enables IDDT test generation at logic level.The Bayesian optimization algorithm is utilized for IDDT test generation.Experimental results show that about 25% stuck-open faults are with IDDT testability larger than 2.5,and likely to be IDDT testable.It is also found that most IDDT testable faults are located near the primary inputs of a circuit under test.IDDT test generation does not require fault sensitization procedure compared with stuck-at fault test generation.Furthermore,some redundant stuck-at faults can be detected by using IDDT testing.     

基于云计算的智能测试保障体系构建

针对当前武器装备系统复杂以及测试保障难度大的问题,提出基于云计算的装备智能测试保障体系。该体系以云化智能测控网及运行其上的人工智能算法组成的云计算平台为基础,结合装备的自主保障流程,设计一种基于认知的智能测试与保障方法,实现装备的智能测试与自主保障。基于认知的智能测试以装备的测试性设计为前提,包含机内测试和机外测试两种方式,其运行原理相同,通过云化智能测控网,依托云计算,对获得的历史数据和实时数据进行自组织学习,实时调整装备测试机制、数据传输机制和数据分析与故障预测机制,为实现装备的自主保障提供智能决策支持。     

输入端加译码器的可编程逻辑阵列的复杂性分析

输入端加译码器的可编程逻辑阵列比普通的可编程逻辑阵列具有更大的实现能力。这种阵列表现为三级或－与－或电路。本文提出了与该电路相关的一系列基本概念和理论，并且还进行了复杂性分析，结论是使用该阵列实现一个任意Ｎ变量逻辑函数所需的最大存储单元数为：（２ｎ＋１）２＾ｎ－２．     

A measurement framework for object-oriented software testability

Testing is an expensive activity in the development process of any software system. Measuring and assessing the testability of software would help in planning testing activities and allocating required resources. More importantly, measuring software testability early in the development process, during analysis or design stages, can yield the highest payoff as design refactoring can be used to improve testability before the implementation starts.

This paper presents a generic and extensible measurement framework for object-oriented software testability, which is based on a theory expressed as a set of operational hypotheses. We identify design attributes that have an impact on testability directly or indirectly, by having an impact on testing activities and sub-activities. We also describe the cause-effect relationships between these attributes and software testability based on thorough review of the literature and our own testing experience. Following the scientific method, we express them as operational hypotheses to be further tested. For each attribute, we provide a set of possible measures whose applicability largely depends on the level of details of the design documents and the testing techniques to be applied. The goal of this framework is twofold: (1) to provide structured guidance for practitioners trying to measure design testability, (2) to provide a theoretical framework for facilitating empirical research on testability.