基于多级离散余弦变换的鲁棒数字水印算法

将多级离散小波变换的"多级"思想引入到离散余弦变换中,并对多级离散余弦变换的特性进行了分析,在此基础上提出了一种基于多级离散余弦变换的数字水印算法,该算法从多级离散余弦变换系数中选择适当的位置嵌入水印信息.实验结果表明文中算法的鲁棒性优于常规基于离散余弦变换的数字水印算法,并且它的实时性不受多级变换的影响.此外,该文对多级离散余弦变换中变换系数和变换级数的选择进行了研究,实验结果表明合理选择变换系数进行二级变换可以获得最佳性能.     

二维离散分数余弦变换的改进形式

将一维离散余弦变换的变换核扩展到二维分数形式,得到Pei形式的二维离散分数余弦变换。通过整数阶余弦变换的线性叠加构造一种改进形式的二维离散分数余弦变换,并基于特征值和特征向量理论,分析2种离散分数余弦变换的周期关系。数值仿真结果表明,2种形式可以达到相同的变换结果,适用于图像编码、数字水印等领域。     

计算一类数字变换的收缩阵列

本文以DFT的收缩(Systolic)阵列结构为基础,给出了一类数字变换在这种结构上的VLSI并行实现,这些变换包括离散富里叶变换,离散余弦变换,离散正弦变换,离散Hartley变换,数论变换和多项式变换。这些基本的阵列结构是构造大规模收缩阵列的基础。     

基于Radon变换和多级离散余弦变换的鲁棒性水印算法

将contourlet变换和多级离散小波变换的 "多级" 概念引入到离散余弦变换中,并针对当前传统的离散余弦变换域水印算法不能有效旋转几何攻效抵抗击行进了特性的分析和改进.在此基础上提出了一种基于Radon变换和多级离散余弦变换的鲁棒性水印算法,该算法首先从多级离散余弦变换系数中选择适当的位置嵌入水印信息;同时在水印检测之前,利用Radon变换检测算法对待检测图像进行几何校正,然后提取水印信息.实验结果表明本文算法的鲁棒性优于常规基于离散余弦变换的数字水印算法,并且它的实时性不受多级变换的影响.     

基于DWT及DCT的数字图像水印综述

综述了基于离散小波变换及离散余弦变换的数字图像水印算法．由于小波变换具有良好的局部性时频分析特性和多分辨率分析,而离散余弦变换具有良好的聚能效应,因此两者在图像水印领域有很好的应用效果．对基于两种变换的数字水印技术的相关概念和现有方法进行了描述与分析,同时总结了两类算法优缺点,并讨论了几种可能的解决策略。另外,对基于两种变换的数字图像水印技术的未来发展方向和前景进行了预测。     

基于离散余弦变换与独立方量分析的音频数字水印

提出了一种基于独立分量分析(IndependentComponentAnalysis)的音频数字水印方法。嵌入时,对原始音频文件进行离散余弦变换,在变换得到的音频文件中利用随机混合嵌入已进行压缩编码的水印图像后进行离散余弦逆变换。提取时,对音频文件进行离散余弦变换,独立分量分析方法进行水印检测。实验结果表明这种方法的强鲁棒性和可行性。     

离散余弦变换在轴承故障诊断中的应用

针对轴承故障难以快速诊断的问题,提出了基于离散余弦变换(DCT)和Hilbert变换提取轴承损伤的特征信息新方法。首先采用离散余弦变换对时域信号进行处理获得系数,再合理选择离散余弦变换系数重构信号,用Hibert包络分析重构信号并从中提取特征频率。实际应用表明,该方法能快速、准确地检测出轴承损伤,可有效应用于轴承故障的在线监测与诊断。     

图形硬件通用计算技术的应用研究

在通用计算的图形硬件加速研究中,综合了在OPENGL体系下的计算模型。通过实验,测试了该计算结构的性能并分析了提高计算性能的一些方法。在此基础上,介绍一种基于GPU的并行计算二维离散余弦变换方法。该方法可在GPU上通过一遍绘制,对一幅图像1至4个颜色通道,同时进行8×8大小像素块的离散余弦变换。实验表明在该实验硬件基础上,采用GPU加速的并行离散余弦变换,可比相同算法的CPU实现提高数百倍。     

基于离散余弦变换的光栅投影图的压缩研究

文中研究了基于离散余弦变换的光栅投影图的压缩。首先介绍了三维形貌测量的光栅投影图,及其需要进行压缩的原因。接着讨论了可用于图像压缩的离散余弦变换技术,推导出对于光栅图进行离散余弦变换只保留第一列或第一行系数就可以完整重构光栅图的结论。利用此结论创建用于压缩的二值掩模矩阵,并对光栅投影图之一的位相图进行基于离散余弦变换的压缩。实验结果表明此方法能有效地压缩位相图,使用压缩后还原的位相图解调出来的物体形貌信息能得到有效的保留。     

DCT专用芯片A121及其在ADCT图象编译码器中的应用

介绍了离散余弦变换的原理及其专用集成电路芯片Ａ１２１的结构与特性，对实现自适应离散余弦变换图象编码的具体算法作了讨论。给出Ａ１２１在ＡＤＣＴ图象编译码器中实际应用的例子。该编译码器以Ａ１２１为核心，采用８０９８作控制器，灵活地实现图像编，解码的ＡＤＣＴ运算。     

Design of algorithm-based fault-tolerant multiprocessor systems forconcurrent error detection and fault diagnosis

Algorithm-based fault tolerance (ABPT) is a low-overhead system-level concurrent error detection and fault location scheme for multiprocessor systems. We present new methods for the design of ABFT systems. Our design procedure is applicable to a wide range of systems in which processors share data elements. A feature of our design approach is that the type of checks to be used in the final system can be controlled by the system designer. We also present some new bounds on the number of checks needed in ABFT system design     

A novel concurrent error detection scheme for FFT networks

The algorithm-based fault tolerance techniques have been proposed to obtain reliable results at very low hardware overhead. Even though 100% fault coverage can be theoretically obtained by using these techniques, the system performance, i.e., fault coverage and throughput, can be drastically reduced due to many practical problems, e.g., round-off errors. A novel algorithm-based fault tolerance scheme is proposed for fast Fourier transform (FFT) networks. It is shown that the proposed scheme achieves 100% fault coverage theoretically. An accurate measure of the fault coverage for FFT networks is provided by taking the round-off error into account. The proposed scheme is shown to provide concurrent error detection capability to FFT networks with low hardware overhead, high throughput, and high fault coverage     

Graceful degradation in algorithm-based fault tolerantmultiprocessor systems

Algorithm-based fault tolerance (ABFT) is a technique which improves the reliability of a multiprocessor system by providing concurrent error detection and fault location capability to it. It encodes data at the system level and modifies the algorithm to operate on the encoded data in order to expose both transient and permanent faults in any processor. Work done till now in this area takes care of only the fault detection and location part of the problem. However, if spare processors are not available, then after a faulty processor has been located, the work initially assigned to it has to be mapped to some nonfaulty processors in the system in such a way that the fault tolerance capability of the system is still maintained with as small a degradation in performance as possible. In this paper, we propose an integrated deterministic solution to the above problem which combines concurrent error detection and fault location with graceful degradation. There exists no previous deterministic ABFT method for the design of general t-fault locating systems, even for the case of t=1. We propose a general method for designing one-fault locating/s-fault detecting systems. We use an extended model for representing ABFT systems. This model considers the processors computing the checks to be a part of the ABFT system, so that faults in the check computing processors can also be detected and located using a simple diagnosis algorithm, and the checks can be mapped to other nonfaulty processors in the system     

椭圆曲线点乘的抗故障攻击FSM控制器设计

为提高有限状态机(FSM)控制器的抗故障攻击能力,提出一种非并发故障检测方案。方案利用线性码的故障检错特性,通过在状态机电路中建立故障传播路径来实现。设计了基于NAF编码的从左至右扫描点乘算法的安全有限状态机电路,并对该电路进行了仿真验证与分析。通过仿真验证,与并发故障检测方案相比,该设计能够在减少状态机频繁译码工作量的情况下,正确检测错误并报警,提高了抗故障攻击能力。     

一种离散余弦变换电路的并发故障检测结构…

本文提出了一种离散余弦变换 (DCT)电路的并发故障检测结构。DCT采用 B.G.L ee算法蝶型结构实现 ,检测采用的方法是基于算法的并发故障检测容错方法。与其它并发故障检测容错结构相比 ,本文提出的并发故障检测 DCT结构在硬件及时间冗余度上均优越     

Analysis and randomized design of algorithm-based fault tolerantmultiprocessor systems under an extended model

Reliability of compute-intensive applications can be improved by introducing fault tolerance into the system. Algorithm based fault tolerance (ABFT) is a low-cost scheme which provides the required fault tolerance to the system through system level encoding. In this paper, we propose randomized construction techniques, under an extended model, for the design of ABFT systems with the required fault tolerance capability. The model considers failures in the processors performing the checking operations     

Using Data Flow Information to Obtain Efficient Check Sets for Algorithm-Based Fault Tolerance

Algorithm-Based Fault Tolerance (ABFT) is a well known technique for achieving fault and error detection in multiprocessor systems. We examine several issues concerning ABFT systems when the data flow information for the underlying multiprocessor computation is available. Our results show that this finergrained information can be exploited to obtain test schemes involving fewer checks, in some cases, dramatically fewer checks. We address both the analysis and design of ABFT systems when the data flow information is available. The analysis problem for a given ABFT system is to determine the fault detectability and the fault locatability (maximum number of detectable and locatable faulty processors) of the system. We show that the analysis problem can be solved efficiently when the number of faults is fixed. We also address the computational difficulty of this problem when the number of faults is not fixed. The design problem is concerned with the construction of a minimal collection of checks which can detect or locate a specified number of faults for a given multiprocessor computation. We examine some special classes of data flow graphs and establish upper and lower bounds on the number of checks needed to detect or locate a given number of faults. We also address the computational difficulty of this design problem for several cases.     

数字电路并发差错检测的新概念

并发差错检测是提高数字电路与系统可信的重要技术。文中建立了一种基于并发差错检测电路的结构模型。它由实现电路基本功能的基本功能模块和实现电路并发差错检测功能的检测器部分联所构成;提出了表征基于部分自校验概念的并发差错检测机制的一组新概念：精简强故障保险、精简强变量分离、精简强自校验、ｋ－容错精简强故障保险、ｋ－容错精简强变量分离和ｋ－容错精简强自校验,并研究了数字电路并发差错检测的主要概念之间的关系     

AES算法的并发错误检测方法及其VLSI实现

提出了一种AES算法的抗差分差错分析的并发错误检测方法--二维奇偶校验方法.与原有的一维奇偶校验方法相比,该方法提供了更为优化的奇偶校验位设置,更重要的是能够同时检测水平和垂直方向上的奇数个错误,在保持了对单个错误的100%的覆盖率的同时,将对多个错误的覆盖率大大提升.由于水平和垂直校验位计算模块可以复用,因此与原有的一维奇偶校验方法相比,该方法增加的硬件开销很小,对硬件实现的关键路径和吞吐率都没有影响,是一种理想的低成本高效率的抗差分差错分析的并发错误检测方法.     

Synthesis of algorithm-based fault-tolerant systems from dependencegraphs

Algorithm-based fault tolerance (ABFT) is a method for improving the reliability of parallel architectures used for computation-intensive tasks. A two-stage approach to the synthesis of ABFT systems is proposed. In the first stage, a system-level code is chosen to encode the data used in the algorithm. In the second stage, the optimal architecture to implement the scheme is chosen using dependence graphs. Dependence graphs are a graph-theoretic form of algorithm representation. The authors demonstrate that not all architectures are ideal for the implementation of a particular ABFT scheme. They propose new measures to characterize the fault tolerance capability of a system to better exploit the proposed synthesis method. Dependence graphs can also be used for the synthesis of ABFT schemes for non-linear problems. An example of a fault-tolerant median filter is provided to illustrate their utility for such problems