How RISCy is DSP?

The characteristics of benchmark digital signal processing (DSP) algorithms are examined. These characteristics are used to suggest the features of an ideal DSP architecture, which is compared to current DSP and reduced instruction set computer (RISC) architectures. Timing comparisons taken from data books and research show that several on-the-market RISCs have a DSP performance close to or better than some DSP chips. Analysis of these DSP and RISC architectures leads to the suggestion of an ideal low-cost RISC DSP chip     

DSP体系结构发展的新趋势

CISC→RISC设计思想对DSP体系结构设计中数据和指令级并行性开发产生了深刻影响，融合RISC和SIMD技术的单核处理器已经成为DSP体系结构设计的新趋势。     

Architecture for video coding on a processor with an ARM and DSP cores

This paper aims to describe architecture for video coding on a processor with an ARM and DSP cores. The proposed platform has been designed for MPEG-4 Visual Simple Profile. The obtained results are optimized if compared with these of single-core. The dual-core processors, composed of RISC and DSP, are widely used as the based-band processors of cell phones. The RISC suits for IO control, while DSP is useful for computation. The operational efficiency of the integration of RISC and DSP is outstanding. Video compression requires a great deal of computation, so we take both the feature of coding algorithm and the hardware platform into consideration. We analyze features of key components in video codec and propose the framework, which adopts DMA to shorten the time needed. It is the result of the communication between the dual-cores. The experimental results indicate that during the inter-frame processing, dual-core with DMA can cut down the processing time by 1/4 more than that of single-use of ARM or DSP. Moreover, it can save 3/4 of the time for encode/decode processing in inter-frame. Especially, in respect of motion estimation, the performance rating can be improved by 4 times.     

Assigning service requests in Voice-over-Internet gateway multiprocessors

New and proposed communication systems are entirely digital, including Voice over Internet Protocol tasks as well as traditional data packets, fax, etc. Numerous digital signal processing (DSP) algorithms are available to encode and decode these signals, each having different requirements for data memory, program memory, and processor speed. A DSP multiprocessor having numerous DSP cores receives a stream of requests for encoding and decoding tasks. A service request is “blocked” if no DSP core can handle the task when it arrives. We present algorithms for assigning DSP tasks to cores in order to minimize the number of blocked tasks. This is similar to an online bin-packing problem with the important difference that the program memory can be shared between simultaneous service requests for the same DSP algorithm. Since bin-packing is known to be NP-complete, we develop fast heuristic online methods for this problem.     

GCC在高性能微处理器DSP和CPU上的移植

在分析GCC结构的基础上,总结了GCC在高性能微处理器DSP和CPU上移植的解决方案,并比较了DSP、CPU和RISC结构的处理器在移植上的差别,重点介绍了GCC对DSP和CPU信号处理功能的支持以及指令分组和指令执行分组在GCC中的实现。     

一种基于异构多核DSP的IEEE 802.11a接收端基带处理的研究和实现*

现有基于异构多核DSP的IEEE 802.11a接收端实现方法中DSP核空闲等待时间较长,不能充分体现多核DSP的高性能计算能力。结合多核DSP的特点,通过核内细粒度流水和核间粗粒度流水的方法,来提高多核DSP的执行效率,并在目标异构多核DSP上实现完整的IEEE 802.11a接收端基带处理。实验结果表明,该方法不仅能满足系统吞吐量和实时性,与类似工作相比还能保证较高的DSP核平均利用率。     

FPGA–DSP co-processing for feature tracking in smart video sensors

Motion estimation in videos is a computationally intensive process. A popular strategy for dealing with such a high processing load is to accelerate algorithms with dedicated hardware such as graphic processor units (GPU), field programmable gate arrays (FPGA), and digital signal processors (DSP). Previous approaches addressed the problem using accelerators together with a general purpose processor, such as acorn RISC machines (ARM). In this work, we present a co-processing architecture using FPGA and DSP. A portable platform for motion estimation based on sparse feature point detection and tracking is developed for real-time embedded systems and smart video sensors applications. A Harris corner detection IP core is designed with a customized fine grain pipeline on a Virtex-4 FPGA. The detected feature points are then tracked using the Lucas–Kanade algorithm in a DSP that acts as a co-processor for the FPGA. The hybrid system offers a throughput of 160 frames per second (fps) for VGA image resolution. We have also tested the benefits of our proposed solution (FPGA + DSP) in comparison with two other traditional architectures and co-processing strategies: hybrid ARM + DSP and DSP only. The proposed FPGA + DSP system offers a speedup of about 20 times and 3 times over ARM + DSP and DSP only configurations, respectively. A comparison of the Harris feature detection algorithm performance between different embedded processors (DSP, ARM, and FPGA) reveals that the DSP offers the best performance when scaling up from QVGA to VGA resolutions.     

基于SPM的多核SoC访存结构设计与优化

针对“一个RISC主处理器核＋几个专用协处理器核”结构的计算密集型SoC,设计一种以执行命令方式完成大块数据传输的高效访存结构。通过增加组传输和流水传输模式,对该结构进行优化。实验结果表明,该访存结构设计及优化方案的数据传输效率高、实现开销小,并且对同类SoC系统,该设计具有良好的适用性。     

支持细粒度并行性开发的多核DSP快速核间通信机制

一些数字信号处理程序存在强数据相关性,在将这些数字信号处理程序划分到多核DSP上时,需要开发细粒度并行性,而细粒度并行性的开发需要快速的核间通信机制支持。本文提出了一种新的面向多核DSP的快速核间通信机制:标记式共享寄存器文件TSRF,TSRF由所有的DSP核共享,寄存器文件中的每个寄存器同一个有效标记位关联,该标记位提供了核间通信同步支持。本文构建了集成TSRF机制的多核DSP原型的周期精确模拟器,该多核DSP原型包含的处理器核数目为4个。通过详细模拟,我们使用数据相关性较强的数字信号处理算法:IIR滤波和ADPCM编解码,对TSRF机制的性能进行了测试,与单核DSP相比,TSDB机制性能提升分别为1.8、1.2和1.9左右。     

片上Trace辅助的嵌入式多核程序分析与调优

YHFT-QDSP是一款多核处理器,TraceDo是其实时片上追踪调试系统。本文首先将串行二维快速傅立叶变换算法(2D-FFT)并行化,映射于该多核处理器;并基于可视化的TraceDo系统,从多核程序同步及核间数据传输两个方面深入分析了并行2D-FFT程序行为;而后提出并实现了两种性能优化(调优)方案。实例研究表明,TraceDo系统可有效地提高嵌入式多核程序的开发效率。     

多核DSP的Nand Flash启动软硬件设计

多核处理器片内一般具有容量较大的动态RAM,其程序代码存储在片外Flash中,或者通过主机下载程序。多核DSP的启动和单核启动区别较大,本文以8核DSP芯片TMS320C6678为应用平台,介绍了多核DSP的启动方法。通过I2 C总线芯片存储一级启动程序,应用程序存储到容量较大的Nand Flash芯片,文中详细介绍了该启动方法的软硬件设计。     

基于DSP+FPGA的实时信号采集系统设计与实现

为了提高对实时信号采集的准确性和无偏性,提出一种基于DSP+FPGA的实时信号采集系统设计方案。系统采用4个换能器基阵并联组成信号采集阵列单元,对采集的原始信号通过模拟信号预处理机进行放大滤波处理,采用TMS32010DSP芯片作为信号处理器核心芯片实现实时信号采集和处理,包括信号频谱分析和目标信息模拟,由DSP控制D/A转换器进行数/模转换,通过FPGA实现数据存储,在PC机上实时显示采样数据和DSP处理结果;通过仿真实验进行性能测试,结果表明,该信号采集系统能有效实现实时信号采集和处理,抗干扰能力较强。     

Programmable DSPs: a brief overview

A brief history of digital signal processors (DSPs), which may become the key to the integration of telecommunications and computation, is presented. A tabular summary of models to date is provided. The recent emergence of DSP cores is discussed     

DSP在水声定位信标中的应用

由于DSP在信号处理和功能实现上的优势,水声定位信标可选用DSP作为核心部件,利用它来开发系统功能。本文介绍了水声定位信标关键功能基于DSP进行设计与实现的情况,同时对信标的工作原理和DSP板也作了简单的介绍。     

基于DSP和LabVIEW的高压真空断路器机械特性在线监测系统的研制

文章提出了一种基于DSP和LabVIEW的高压真空断路器机械特性在线监测系统的设计方案。该系统的下位机数据采集系统以DSP为核心,通过传感器、信号调理电路等完成对高压真空断路器机械特性参数、分合闸电流信号和振动信号的采集,可实现就地显示及通过CAN总线将数据传送至上位机进行分析、显示;上位机管理系统以LabVIEW为开发平台,利用其图形显示功能和与Matlab通信功能实现了对测量数据的显示、分析及处理。现场测试结果表明,该系统运行稳定,准确性较好。     

磁通门测量地磁信号的数字化分析

针对现有的磁通门信号处理电路仍以模拟元件为主,电路较为复杂的缺点,提出了一种以数字信号处理器(DSP)为主的信号处理系统,优化磁通门传感器的结构,提高了磁通门传感器的抗干扰能力.根据双磁芯磁通门的基本原理,建立了磁通门数学模型并采用Simulink信号处理模块模拟DSP对磁通门输出信号进行处理;针对双磁芯磁通门上、下磁芯不一致产生的磁通门信号噪声,采用带通滤波方法进行了滤波,仿真结果与理想状态下双铁芯磁通门的输出一致,系统分辨力达到3 nT.通过实验数据与仿真数据的对比,验证了DSP信号处理系统的可行性.     

归一化互相关灰度图像匹配的多核信号处理器实现

为了满足图像处理对处理器性能的高要求,以基于灰度的归一化互相关(NCC)匹配算法为例,采用高性能、低功耗的多核数字信号处理器(DSP)系统,根据归一化互相关算法中模板图像在源图像中逐个像素搜索并计算相关性的特点,将搜索区域分成六个部分并使TMS320C6472的六个核并行搜索计算这六个区域,并在不同图像存储位置采用不同图像和模板大小实现了多核DSP归一化互相关图像匹配算法。实验结果表明,多核DSP具有作为数字信号处理器的高速信号和图像处理的特点,同时可以根据不同算法通过核间任务分配实现多核并行处理。对于归一化互相关灰度图像匹配算法,TMS320C6472六核DSP和单核DSP比较获得接近单核DSP六倍的性能,对于较大尺寸的图像和PC相比也具有一定的性能加速。     

支持视频标签的网络视频监控系统

采用TI公司的TMS320C6713型号DSP开发板和三星公司的2410开发板设计了一个嵌入式网络视频监控系统.实时视频监控数据量多,压缩的计算量较大,采用DSP进行压缩可以发挥其速度快的特点.为了方便视频数据的传输和存储,实现监控系统的网络化,在ARM上移植嵌入式Linux来满足要求.同时该系统在客户端支持对视频数据的检索,用户可以快速找到自己想要观看的视频点,不必去浏览整个视频文件.     

基于激光测距仪的3 维景深图像重构与辨识

针对3 维景深图像仅仅具有距离信息的局限性,提出景深面元的概念,并利用基于景深面元的法向 量聚类法对景深图像进行基本的识别．通过景深面元,将Sobel 算子引入到景深图像的边缘检测上来,提出了一 种简易的景深图像边缘识别方法．为了满足3 维景深图像重构和识别的实时性要求,采用了ARM（advanced RISC machine）+ DSP（digital signal processing）的硬件平台架构．实验结果表明,基于景深面元的3 维识别和边缘检测算 法是有效可行的．     

频谱仪多种内核间通信机制的方案设计

手持式频谱仪系统采用的是ARM、DSP、FPGA的三核架构。对于多核架构,保证内核间的通信尤为重要。对于内核间通信,首先是对通信接口的硬件设计与通信机制的研究,然后着重介绍ARM支持下的嵌入式Linux的接口设备驱动的开发,包括通信接口HPI、SPI的驱动。最后完成驱动测试,整个系统运行稳定。