NoC节点编码及路由算法的研究

NoC的设计和实现受到芯片的面积、功耗、深亚微米效应的限制.将拓扑结构和节点编码相结合,提出一种基于约翰逊码的二维平面编码.该编码隐含了Torus网络拓扑结构以及网络节点之间的连接关系并且有很好的扩展性,能够简化Torus拓扑结构上路由算法的实现和降低硬件成本.基于此编码和利用X-Y路由的路由确定性特点,提出改进X-Y路由,在中间节点只需要3或5个逻辑运算,降低路由的计算复杂性和硬件成本.最后,进行了节点结构设计.提出的编码不仅用于NoC的路由方面而且在NoC任务映射方面有重要应用.     

片上网络的低功耗自适应数据保护

针对片上网络(NoC)提出了一种低功耗自适应数据保护机制。根据不同的片上网络通信链路错误数目自适应选择，在路由节点之间进行数据保护的跳距，保证了系统芯片功耗效率最优化。实验结果证明，在同样的可靠约束条件下，采用自适应数据保护，其功耗低于节点到节点，端到端的数据保护，特别是对需要高可靠性的NoC通信结构，自适应数据保护机制表现得更为有效。     

基于报文检测的快速自适应NoC容错路由算法

传统的自适应片上网络(NoC)容错路由算法采用一步一比较的方式来确定最优端口, 未能有效降低传输延迟。根据数据包在2D Mesh NoC前若干连续的跳数内最优端口固定的特点, 提出了一种基于报文检测的快速(FPIB)自适应容错路由算法。算法采用跳步比较的方式来减少数据包的路由时间, 并使用模糊优先级策略来进行容错路由计算。实验结果表明, 与uLBDR容错路由算法相比, 该算法能有效地降低平均延迟, 且实现算法的硬件开销更低。     

通过器件共享实现的双向无阻塞光互连片上网络

在片上网络NoC( Network-on-Chip)中,通过光通信取代传统的电信号传精来获得低延时、低功耗成为一种新兴的研究方向—光五连片上网络ONoC(Optical Network-on-Chip)本文提出一种全新的双向传输的波长路由片上网络,这种新的结构对调制好的光信号的波长进行判断来实现在网络节点之间的路由,同时还能够通过器件和传输通道的共享实现数据的双向传输.和传统的电信号传输网络相比,本文提出的双向传输结构减少了50％的硬件开销和70％的芯片面积开销,提高了器件利用率,降低了网络传输延时,极大地提高了网络传精性能,对于光互连片上网络具有重要意义.     

GcChord:基于组和缓存的改进型DHT网络

在基于DHT技术的对等网络中,一个重要的研究内容是减少逻辑网络和物理网络不匹配所带来的寻路时延过长的问题。文章提出一种利用组来匹配物理网络,利用超级节点缓存查询和地址信息,并且在普通节点收到查询请求时缓存查询源节点地址信息的路由算法GcChord(Group Cache based Chord)。仿真结果表明,GcChord的路由性能优于Chord系统,并且节点重复(有一定倾向)查询越多,其平均物理、逻辑跳数越少。     

PRDT（2，1）架构的NoC系统容错路由算法

链路和节点的故障会导致网络中许多节点无法相互通讯,因此容错性是NoC系统设计中的一个重要问题。基于一种新的NoC网络拓扑结构PRDT（2,1）,提出一种PRDT（2,1）容错路由算法以及相应的节点失效算法。节点失效算法通过使较少数量的无故障节点失效来构造矩形故障区域,PRDT（2,1）容错路由算法仅使用了最小数量的虚拟通道并提供足够的自适应性以实现无死锁容错路由。只要故障区域没有断开网络,这一算法能够保证路由的连通性。算法在不同故障率的PRDT（2,1）网络中仿真,结果显示这一算法具有良好的平滑降级使用特性。     

基于物理拓扑的改进Chord模型

针对结构化点对点模型中物理拓扑与逻辑拓扑不匹配的现象,结合Chord模型和混合Chord模型,提出一种基于物理拓扑的改进模型。利用网络区域性,在每个自治系统内选择度数最大的节点作为超级节点(SN),不同SN在上层构成Chord环,从而使模型的逻辑拓扑与网络物理拓扑相吻合,减少资源定位和访问的路由跳数。实验结果表明,该模型能减少平均路由跳数、降低平均时延。     

基于超立方体拓扑结构的NoC测试规划研究

为了优化测试时间,提高片上网络(NoC)资源内核的测试效率,结合NoC测试特点,提出一种基于超立方体拓扑结构的NoC测试规划优化方法。该方法针对超立方体结构自身优势设计一种具有部分自适应能力的E-cube路由算法,增加测试过程中对路由节点和通信链路的利用率;通过引入混度序列和压缩因子对粒子算法进行改进,增加种群多样性。在ITC’02国际标准电路测试集上进行对比实验,结果表明,与其他方法相比,该方法测试时间最大优化率可达17.38%,有效缩短了测试时间。     

一种基于物理网络拓扑的高效Chord模型

在结构化P2P系统中,建立逻辑overlay时没有考虑底层物理网络拓扑结构,其路由机制主要是根据节点逻辑上的相邻性进行设计,导致物理网络邻近节点的延迟较大。该文在Chord 基础上提出一种P-Chord系统模型,利用物理网络的拓扑结构,在节点路由表中增加了邻居表,实验证明P-Chord在路由延迟和覆盖网络的跳数上相比Chord都有较好的改善。     

UWSNs中基于深度的抑制空洞路由优化算法

针对传统的水下无线传感器网络(UWSNs)的位置路由存在路由空洞问题,提出了基于深度的抑制空洞路由(DSVR)的UWSNs路由协议.DSVR协议通过融合跳数、物理距离和邻居数多个指标决策路由.为了提高通信可靠和缓解路由空洞,DSVR协议选择具有最小跳数路径、最少邻居数的节点作为下一跳转发节点.同时,DSVR协议利用定时器抑制冗余数据包.仿真结果表明:提出的DSVR协议能有效地提高数据包传递率,并降低端到端传输时延以及能耗.     

复合型路由器级拓扑模型

针对HOT模型的路由器级拓扑在大规模节点下的不足,通过结合自治域级拓扑和路由器级拓扑两种方法,实现了一种复合型Internet路由器级拓扑模型A2R。A2R模型仅依靠路由器规模完成网络拓扑图,解决了自治域拓扑间商业关系推测依靠BGP表的问题,以及自治域间路由连接的问题。实验证明A2R拓扑模型在大规模节点下比其他路由器级拓扑模型拥有更好的性能。     

一种面向大规模网络拓扑发现的研究

由于互联网路由存在不对称的特点,即“源-宿”方向和反方向路由路径的不一致,使得已有的拓扑发现算法存在路径丢失问题。增加测量点会增加流量负荷。利用源-宿双向测量的方法,解决了拓扑发现中的路径丢失。实验结果表明该算法不仅可以获得较高的发现率,还具有网络流量负荷小的特点。     

Enhancing data security in ad hoc networks based on multipath routing

An ad hoc network is a self-organizing network of wireless links connecting mobile nodes. The mobile nodes can communicate without an infrastructure. They form an arbitrary topology, where the nodes play the role of routers and are free to move randomly.     

Topology design of switched enterprise networks using a fuzzy simulated evolution algorithm

The topology design of switched enterprise networks (SENs) is a hard constrained combinatorial optimization problem. The problem consists of deciding the number, types, and locations of the network active elements (hubs, switches, and routers), as well as the links and their capacities. Several conflicting objectives such as monetary cost, network delay, and maximum number of hops have to be optimized to achieve a desirable solution. Further, many of the desirable features of a network topology can best be expressed in linguistic terms, which is the basis of fuzzy logic. In this paper, we present an approach based on Simulated Evolution algorithm for the design of SEN topology. The overall cost function has been developed using fuzzy logic. Several variants of the algorithm are proposed and compared together via simulation and experimental results are provided.     

基于traceroute的层析成像方法*

针对传统的网络拓扑识别方法（如traceroute）无法完成包含不协作节点的拓扑识别以及基于网络层析成像技术的拓扑识别方法的复杂性和不确定性问题,提出一种基于traceroute的层析成像技术的拓扑识别方法。该方法可通过提出的最小相似度聚类算法和匿名节点构造归并算法,将网络层析成像获得的拓扑信息与trace-route探测结果融合,构成最终的拓扑结构。NS2的仿真表明,该方法不仅可识别包含不协作节点的网络拓扑,且所使用的探测包的数量也大大减少。     

Designing power and performance optimal application-specific Network-on-Chip architectures

This paper presents an optimal method for topology synthesis by taking into account factors related to power, performance, and contention in an application-specific Network-on-Chip (NoC) architecture. A Tabu search based approach is used for topology generation with an automated design technique, incorporating floorplan information to attain accurate values for power consumption of the routers and physical links. The Tabu search method incorporates multiple objectives and is able to generate optimal NoC topologies which account for both power and performance. The contention analysis technique assesses performance and relieves any potential bottlenecks using virtual channel insertion after considering its effect on power consumption and performance improvement within the NoC. The contention analyzer uses a Layered Queuing Network approach to model the rendezvous interactions among system components. Several experiments are conducted using various SoC benchmark applications to compare the power and performance outcomes of the proposed technique.     

Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs

Rapid growth in the number of Intellectual Property (IP) cores in System-on-Chip (SoC) resulted in the need for effective and scalable interconnect scheme for system components – Network-on-Chip (NoC). Router is a key component in an NoC design that impacts the overall area utilization. It is crucial to evaluate the area efficiency of NoC routers. In this paper, we evaluate and compare two recent NoC routers for Field Programmable Gated Arrays (FPGAs). The first one is generated using the automated NoC synthesis tool CONfigurable NEtwork Creation Tool (CONNECT). The second one is an NoC router manually designed using VHDL and synthesized Altera Quartus II CAD tool. Three NoC topologies namely ring, mesh and torus are used for evaluating the two routers based on area utilization metric. The routers are evaluated by varying the node sizes from 4 to 16 for each topology. For smaller NoC topologies, CONNECT router uses less area but as the NoC size increases manual router design provides up to 85% reduction in area utilization. The results presented in this paper will be useful to designers interested in NoC implementation on FPGAs.     

A collision management structure for NoC deployment on multi-FPGA

With the increasing complexity of algorithms and new applications, the design of efficient embedded systems has to integrate efficient communication structures such as Network-on-Chip. Multi-FPGA platforms are considered to be the most appropriate experimental way to emulate and evaluate these large System-on-Chips. The deployment often goes through the Network-on-Chip partitioning on all FPGAs requiring the use of inter-FPGA communication links between routers. The number of external links and their performance restrict the communication bandwidth. Currently, the number of inter-FPGA signals is considered to be a major problem in the Network-on-Chip deployed on multi-FPGAs. As there are more signals to be connected than IOs, inter-FPGA links must be shared between routers leading to significant bottlenecks. As the ratio of the logic capacity to the number of IOs rises slowly for each FPGA generation, this technological bottleneck will be remaining for future system designs.In this paper, we propose a novel architecture for inter-FPGA collision management in the Network-on-Chip partitioned on multi-FPGAs. The structure ensures to efficiently share the external link between several routers with a minimum number of collisions and inter-FPGA bottlenecks. The proposed architecture is easily placed between the Network-on-Chip and the external protocol. The collision management architecture is based on the BackOff algorithm used in Wi-Fi communications and adapted to FPGA platforms. This algorithm balances accesses among all the routers connected with the inter-board interfacing, thereby avoiding collisions. We compare this structure with traditional techniques using experimental and theoretical results. The novel inter-FPGA architecture for the Network-on-Chip based on the BackOff algorithm achieves lower latency with fewer resources compared to other solutions.     

Cost-Efficient Dragonfly Topology for Large-Scale Systems

It is more efficient to use increasing pin bandwidth by creating high-radix routers with a large number of narrow ports instead of low-radix routers with fewer wide ports. Building networks using high-radix routers lowers cost and improves performance, but also presents many challenges. The dragonfly topology minimizes network cost by reducing the number of global channels required.     

Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions

The simplicity of regular mesh topology Network on Chip (NoC) architecture leads to reductions in design time and manufacturing cost. A weakness of the regular shaped architecture is its inability to efficiently support cores of different sizes. A proposed way in literature to deal with this is to utilize the region concept, which helps to accommodate cores larger than the tile size in mesh topology NoC architectures. Region concept offers many new opportunities for NoC design, as well as provides new design issues and challenges. One of the most important among these is the design of an efficient deadlock free routing algorithm. Available adaptive routing algorithms developed for regular mesh topology cannot ensure freedom from deadlocks. In this paper, we list and discuss many new design issues which need to be handled for designing NoC systems incorporating cores larger than the tile size. We also present and compare two deadlock free routing algorithms for mesh topology NoC with regions. The idea of the first algorithm is borrowed from the area of fault tolerant networks, where a network topology is rendered irregular due to faults in routers or links, and is adapted for the new context. We compare this with an algorithm designed using a methodology for design of application specific routing algorithms for communication networks. The application specific routing algorithm tries to maximize adaptivity by using static and dynamic communication requirements of the application. Our study shows that the application specific routing algorithm not only provides much higher adaptivity, but also superior performance as compared to the other algorithm in all traffic cases. But this higher performance for the second algorithm comes at a higher area cost for implementing network routers.