An improved class of multiplierless decimation filters: Analysis and design

In this paper, we present a class of low-complexity decimation filters for oversampled discrete-time signals. The proposed class of filters improves the frequency response of classical comb filters in two respects. First, it introduces extra-attenuation around the so-called folding bands, i.e., frequency intervals whose spurious signals are folded down to baseband during the decimation process. Second, this class reduces the passband distortion via an effective droop-compensator block, thus increasing the passband of the decimation filters. Like comb filters, the proposed class can be realized through multiplierless architectures, which are also discussed thoroughly in the paper. Unlike comb filters, the proposed filters have superior spurious signal rejection and a greatly reduced droop in the signal passband. These features make the proposed filters suitable for multistage decimation applications, such as reconfigurable software radio receivers, as well as for decimating oversampled digital signals produced by ΣΔ A/D converters.The paper discusses several useful techniques for designing the proposed filters in a variety of architectures with emphasis on non-recursive architectures. Design examples are discussed to highlight the key frequency features along with implementation issues aimed at reducing the computational complexity of the filters.     

一种新型的抽取滤波器设计

文章基于面积和功耗方面考虑提出了一种低功耗多相变级数非递归梳状滤波器结构,这种滤波器适合高阶过采样sigmadeltaA/D转换器。抽取滤波器采用Top-down方法设计,用0.6-μmCMOS标准单元实现,相比同样速度下的标准的非递归结构抽取滤波器节省了约1/3面积和功耗。     

积分清零与积分梳状滤波器在抽取滤波中的应用研究

抽取滤波器的设计是全数字软件接收机中的关键技术,选择合适的抽取滤波器可以使得效率和资源达到最佳的平衡.积分清零和积分梳状滤波器是两种实现简单、滤波性能较好的数字抽取滤波器.这两种滤波器在中频数字接收机中都有重要的应用.从原理上分析和研究了这两种滤波器频域响应,总结了积分梳状滤波器的设计方法.提出了两种滤波器结合应用的方法,并建立模型验证在性能方面的提高.在实际应用中,说明了两者在本质上相同但在结构上的差异,因此在应用中加以区分.通过两种滤波器在相干解调电路和同步电路中的仿真,进一步说明两种滤波器的设计和实现准则.     

Design of CIC roll-off compensation filter in a W-CDMA digital IF receiver

In a digital intermediate frequency (IF) receiver, decimation is performed to reduce the computational complexity and cascaded integrated comb (CIC) filter is used together with the decimation as an anti-aliasing filter. However, the CIC filter generates the roll-off phenomenon in the pass-band, which causes the receiving performance to be considerably degraded due to the distorted pass-band flatness of the receiving filter. In this paper, we propose a design method of the CIC roll-off compensation filter to reduce the performance degradation due to the roll-off characteristics of the CIC filter for a W-CDMA digital IF receiver. The performance of the proposed CIC roll-off compensation filter is confirmed through computer simulation in such a way that bit error rate (BER) is minimized by compensating the roll-off characteristics. In addition, the proposed method can be used in the design of a digital-to-analog (DAC) compensation filter and interpolator in the transmitter.     

The design of energy transfer filters for energy focus filtering

This paper is concerned with extending the energy transfer filters (ETFs) designs to a more general case where the design requirement is to focus signal energy from different input frequency bands into a desired output frequency range. ETFs are a class of non-linear filters recently proposed by the authors to employ non-linear effects to transfer signal energy from one frequency band to a different frequency location. The new ETF designs considered in the present study involve the development of an algorithm for determining output frequencies of non-linear systems subject to an input the frequency components of which are located in two separate frequency intervals and a new procedure for the implementation of the filter design. The results achieved provide an effective approach to the solution to a more general ETF design problem.     

基于脉冲成形扩频信号伪码周期盲估计

针对基带扩频信号的频谱范围较宽,信号在带限的信道中传输时需要对信号进行带宽限制,从而会造成码间干扰和频谱泄露的问题,将基带扩频信号通过脉冲成形器后对其主要参数的抗截获性能进行了研究,并使用两次功率谱的方法对该类信号的伪码周期进行了估计。理论分析证明,做两次功率谱以后的信号以脉冲串的周期来扩展谱线,且信号主要能量将会聚集在一些类似于基带成形脉冲二次谱形状的尖锐脉冲处,通过测量这些尖锐脉冲间的间距即可以估计出基带扩频信号的伪码周期。计算机仿真结果证明,两次功率谱的方法可以在低信噪比的条件下实现对带脉冲成形基带扩频信号伪码周期的估计,且本文算法对伪码周期估计的正确率比文献[1]算法约提高7dB左右。     

用于Sigma—DeltaADC的数字抽取滤波器研究

该文提出了一种对数字抽取滤波器的参数进行自动优化设计的方案。针对降低数字抽取滤波器的面积和功耗,对确定合适的CIC抽取滤波器的级联数目和抽取因子以及半带滤波器的级联数目和阶数进行了讨论和分析。采用上述方案,实现了一个256倍的降频,输入信号采样频率为512kHz,输出信号频率为2kHz,输出信号的信噪比（SNR）为110dB的数字抽取滤波器。最后用Simulink软件进行了仿真验证。     

基于FPGA＋DSP的跳频电台传输系统

高速率跳频、高带宽技术是提高跳频发射机性能的关键,本文结合软件无线电思想和架构,提出一种基于FPGA＋DSP的跳频电台传输系统的设计方案,该系统兼容多种调制方式和跳频速率及数码率。系统采用上下变频器作为系统基带信号与中频信号之间的频率转换器,还给出了系统电路原理图和程序流程图。     

An investigation of speech enhancement using wavelet filtering method

This paper investigates the utilization of wavelet filters via multistage convolution by Reverse Biorthogonal Wavelets (RBW) in high and low pass band frequency parts of speech signal. Speech signal is decomposed into two pass bands of frequency; high and low, and then the noise is removed in each band individually in different stages via wavelet filters. This approach provides better outcomes because it does not cut the speech information, which occurs when utilizing conventional thresholding. We tested the proposed method via several noise probability distribution functions. Subjective evaluation is engaged in conjunction with objective evaluation to accomplish optimal investigation method. The method is simple but has surprise high quality results. The method shows superiority over Donoho and Johnstone thresholding method and Birge-Massart thresholding strategy method.     

Design of New Optimized Architecture Processor for DWT

This paper presents a VLSI implementation of One Dimensional Direct Discrete Wavelet transform (1-D DWT). The DDWT can be viewed as a multi-resolution decomposition of a signal. This means that it decomposes a signal into its components in different frequency bands (octave bands). We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one register bank, four filters, and a control unit. The filters are of different lengths and with new coefficients derived from Daubechies filter coefficients. The designed processor architecture requires no interface circuitry for interconnection to a standard communication bus. The architecture can compute DWT at a data rate of 12×10⁶samples/s corresponding to a typical clock speed of 12 MHz. The architecture is simulated at the gate level in VLSI.     

Methods for the transfer function design of multiple narrow-band bandpass sigma–delta modulators

This paper presents the design analysis of novel tunable narrow-band bandpass sigma–delta modulators, which can achieve concurrent multiple noise-shaping for multi-tone input signals. Four different design methodologies based on the noise transfer functions of comb filters, slink filters, multi-notch filters and fractional delay comb filters are applied for the design of these multiple-band sigma–delta modulators. The latter approach utilises conventional comb filters in conjunction with FIR, or allpass IIR fractional delay filters, to deliver the desired nulls for the quantisation noise transfer function. Detailed simulation results show that FIR fractional delay comb filter-based sigma–delta modulators tune accurately to most centre frequencies, but suffer from degraded resolution at frequencies close to Nyquist. However, superior accuracies are obtained from their allpass IIR fractional delay counterpart at the expense of a slight shift in noise-shaping bands at very high frequencies. The merits and drawbacks of each technique for the various sigma–delta topologies are assessed in terms of in-band signal-to-noise ratios, accuracy of tunability and coefficient complexity for ease of implementation.     

Fractional Fourier domain analysis of decimation and interpolation

The sampling rate conversion is always used in order to decrease computational amount and storage load in a system. The fractional Fourier transform (FRFT) is a powerful tool for the analysis of nonstationary signals, especially, chirp-like signal. Thus, it has become an active area in the signal processing community, with many applications of radar, communication, electronic warfare, and information security. Therefore, it is necessary for us to generalize the theorem for Fourier domain analysis of decimation and interpolation. Firstly, this paper defines the digital fre- quency in the fractional Fourier domain (FRFD) through the sampling theorems with FRFT. Secondly, FRFD analysis of decimation and interpolation is proposed in this paper with digital frequency in FRFD followed by the studies of interpolation filter and decimation filter in FRFD. Using these results, FRFD analysis of the sam- pling rate conversion by a rational factor is illustrated. The noble identities of decimation and interpolation in FRFD are then deduced using previous results and the fractional convolution theorem. The proposed theorems in this study are the bases for the generalizations of the multirate signal processing in FRFD, which can advance the filter banks theorems in FRFD. Finally, the theorems introduced in this paper are validated by simulations.     

利用遗传算法的数字成形滤波器设计方法

数字成形滤波器是数字基带通信系统的重要组成部分。基带信号的频谱范围较宽,频带拥挤问题日益突出,成形滤波技术可以在消除码间干扰（ISI）的前提下,压缩信号频带,提高频谱的利用率。传统的数字滤波器设计包含阶数估计和波纹系数计算两个步骤。而阶数估计方法仅对普通的有限脉冲响应滤波器（FIR）有效,对成形滤波器阶数估计的结果不能达到最优。针对这一问题,将遗传算法的阶数估计和系数计算两个步骤结合起来设计数字成形滤波器,简化了算法复杂度。仿真对比结果表明,该算法在阶数估计和波纹系数计算方面都可以得到更优的结果。     

Comb filters — simulation and design

In this paper a technique in given for the simulation and implementation of comb filters. An apropriate discrete model of the comb filter is choosen and through simulation technique are calculated and optimized its parameters. As it is known comb filters are used for different applications (radars, control systems, e.t.c.) and give really good results. Before the realization the filter is simulated in time and frequency domain and tested through an appropriate computer program such as to obtain the desired frequency response. The used method is the “direct synthesis” of a digital filter.     

基于正交混频的数字下变频技术研究

数字下变频(DDC)是软件无线电的关键技术之一,可以将宽带大数据流信号变成窄带低数据流信号,以便后端DSP实时处理;讨论了基于正交混频的数字下变频实现技术.并将它与直接抽取的数字下变频进行对比,显示出其优势,详细给出了数字振荡控制器(NCO)、信号频谱搬移、抽取前的抗混叠滤波器及整数倍抽取的设计方法;通过对一中频信号进行基于正交混频的数字下变频的仿真试验,结果正确解调出了原始信号;表明这种技术简单可行,有较高的实用价值.     

基于CIC抽取滤波器的谐波分析算法

为消除非同步采样引起的频谱泄漏,提高电网信号的谐波分析精度,提出了基于级联积分梳状(CIC)抽取滤波器的谐波分析算法。在前端AD过采样的情况下,该算法采用逆向搜索的方法实现非同步采样数据的整周期截断,用基于CIC抽取滤波器变频的方法实现信号采样频率与信号基波频率同步,通过快速傅立叶变换(FFT)得到信号频谱,计算基波及各次谐波的幅值和相位。仿真实验结果及误差分析表明,相对于常规的分析方法,该算法具有较高的测量精度。该算法对于非稳态周期信号的谐波分析只需单周期采样,简单易实现,是一种有效的测量方法。     

A digital predistorter for wireless transmitters

A novel digital baseband predistorter with improved reduction of spectral regrowth is proposed and investigated. The improvements are achieved by using a proposed predistortion technique and extended power amplifier (PA) fundamental‐frequency modeling. The digital baseband predistortion (DPD), known for its simplicity of realization, low cost and integrability; however, it suffers from poor linearizing performances. We incorporate baseband iterative injection of in‐band distortion components into the baseband DPD to enhance the nonlinearity compensation. General formulas for the fundamental‐frequency output of a PA with n‐order nonlinearity and recursive formulas for calculating the injected components for different number of iterations are developed. The proposed iterative digital baseband predistorter is verified experimentally with a wireless PA and measured results are presented to demonstrate feasibility of the proposed concept. The spectral regrowth suppression of 20 dB is achieved for a 3.5 MHz digitally modulated signal. © 2009 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

A novel implementation of combined systolic and folded architectures for adaptive filters in FPGA

The adaptive filter constitutes an important part of statistical signal processing. Adaptive filters are often realized either as a set of program instructions running on an arithmetical processing device such as a Microprocessor or Digital Signal Processing (DSP) chip, or as a set of logic operations implemented in a field programmable gate array (FPGA) or in Very Large Scale Integrated Circuit (VLSI). Systolic architecture improves the speed of the system at the cost of increased area. On the other hand, folding technique uses less hardware resources. A combination of systolic and folding structures provides improvement in speed and reduction in area. This paper presents a novel idea of combining Systolic and Folding architectures and its design in various adaptive filters like Recursive Least Square (RLS), Affine Projection (AP) and Kalman filters. The structures are designed using Xilinx System Generator tool of MATlab 2015 and implemented in Xilinx Virtex 5 FPGA. The designed structures are tested for noise cancellation in Electrocardiogram (ECG) signal and results are analysed for various order of all the filters and its metrics are analysed in terms of Signal to Noise Ratio(SNR), Mean Square Error(MSE), area and speed. From the analysis it is observed that the proposed folding in systolic structures improves SNR by 6.77% in RLS, 4.68% in Affine projection and 2.13% in Kalman Algorithm than the conventional structures. It is inferred that the proposed design in Affine projection shows improved SNR than the other filters. The proposed combined folding in systolic architecture shows 18.35% reduction in area and reduction in delay.     

Compact ultra‐wideband bandpass filter with variable notch characteristics based on transversal signal‐interaction concepts

A novel technique is presented to design highly compact microstrip ultra‐wideband (UWB) bandpass filters that exhibit high selectivity quasi‐elliptical response. The design is based on transversal signal‐interaction concepts that enable the inclusion of single or dual notch‐bands within the filter's passband to eliminate interference from other services that coexist within the UWB spectrum. The filter configuration comprises of two transmission paths which include folded T‐shaped stepped impedance resonators (SIRs) that are capacitively coupled with the input/output lines to enable signal transmission. It is shown that by combining the filters of different passband centre frequencies an UWB filter can be realised with either a single‐ or dual‐notch function. The theoretical performance of the filter is corroborated via measurements to confirm that the proposed filter exhibits UWB passband of 123% for a 3 dB fractional bandwidth, a flat group‐delay with maximum variation of less than 0.3 ns, passband insertion loss less than 0.94 dB, high selectivity, a sharp rejection notch‐band with attenuation of ?23 dB, and a good overall out‐of‐band performance. Furthermore, the filter occupies a significantly small area of 94 mm² compared with its classical counterparts. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:549–559, 2014.     

一种零值测试基带信号源设计

北斗是我国自主研发并独立运行的全球卫星导航系统,为了解决北斗导航系统的基带信号调试处理难题,提出了一种零值测试基带信号源设计方案。针对导航系统信号通道多、信号传输速率高且时钟信号精度要求高的特点,单板上集成高性能FPGA和DSP处理器,系统采用模块化设计,采用直接数字射频信号发射技术及高速时钟系统设计,信号源可模拟并输出多制式多路调制基带信号,可完成4通道射频信号采集以及4通道直接射频信号的产生,可灵活配置工作参数及设备工作状态的实时监测。该信号源在北斗导航系统的研发过程中获得成功应用,实验结果表明,该信号源兼备收发两大信号处理链路功能,系统具有通用性强、配置灵活、稳定性好等特点,解决了导航系统领域基带信号调试处理难题。