一种快速的浮点乘法器结构

一种支持IEEE754浮点标准的全流水结构的浮点乘法器被提出．在该浮点乘法器中，提出一种新型的双路浮点乘法结构．这种结构相比于全规模乘法器，在不增加面积的前提下，缩短乘法树关键路径延迟13．6％，提高了乘法器的执行频率．这种乘法器有3个周期的延迟，每个周期能接收一条单精度或双精度浮点乘法指令．使用FPGA进行验证，并使用标准单元实现．采用0．18μm的静态CMOS工艺，执行频率为384MHz，面积为732902．25μm^2．在相同工艺条件下，将这种结构与其他乘法器结构进行比较，结果表明这种结构是有效的．     

CSA/CLA阵列乘法器的测试生成

文中针对最后一级采用４位ＣＬＡ加法器级联的Ｍ×Ｎ位ＣＳＡ／ＣＬＡ阵列乘法器,讨论了一种非常有效的测试生成方法．该方法不依赖于乘法器的大小以及乘法器基本单元内部的具体实现结构,与前人的工作相比,缩短了测试时间．对于上述结构的ＣＳＡ／ＣＬＡ阵列乘法器,使用２８个测试矢量即可得到１００％的故障覆盖率．采用文中给出的测试矢量构造ＣＳＡ／ＣＬＡ阵列乘法器的ＢＩＳＴ电路不需要改变乘法器的结构,因此对乘法器的正常工作性能几乎没有任何影响．     

用复杂可编程逻辑器件的嵌入式阵列实现逻辑设计

描述了复杂可编程逻辑器件FLEX10K10中的嵌入式阵列块EAB的基本原理，分析了如何用多个EAB实现更大规模的乘法器，并且对并行乘法器和时域多选乘法器两种实现方案进行了对比验证。     

基于FPGA的32位并行乘法器的设计与实现

首先分析比较了几种典型的乘法器实现结构，然后采用树型组合方式，对其结构进行了优化，最后在FPGA上设计并实现了一个高性能的32位并行乘法器。     

基于FPGA数字乘法器的设计

数字乘法器是目前数字信号处理中运用最广泛的执行部件之一，本文设计了三种基于FPGA的数字乘法器．分别是移位相加乘法器、加法器树乘法器和移位相加-加法器树混合乘法器。通过对三种方案的仿真综合以及速度和面积的比较指出了混合乘法器是其中最佳的设计方案。     

基于Multisim的模拟乘法器应用电路仿真实验

模拟乘法器能够实现两个模拟信号相乘的非线性器件，在运算和处理电路中有广泛的应用。模拟乘法器不仅可以实现乘法运算，还可以和运算放大器结合实现除法运算和平方根运算，以及进行一元二次方程的求解。采用Multisim软件对模拟乘法器的应用电路进行仿真，简单直观，非常形象，有助于提高学生对《电路与电子》课程的学习兴趣，有利于提高课程的教学质量。     

一种高能效基4-Booth编码并行乘法器设计

常用的卷积神经网络中存在数十亿次乘法运算，神经网络中乘法的大量能耗成为硬件实现神经网络的能效瓶颈之一。为了降低乘法器的能耗，提出了一种高能效基4-Booth编码并行乘法器。通过改进部分积生成模块，消除了传统方法中的补偿位，使得乘法器延时减小且能耗降低。后仿真结果显示，所提出的乘法器比现有乘法器面积减小了5.2%，延时减小了6.3%，能耗降低了10.8%。     

FT-SIMD:一种高性能乘法器的设计

为了提高多媒体数据的处理能力,高性能DSP普遍引入了SIMD技术。作为DSP重要组成部分的乘法器也必须具备这一功能。本文对SIMD乘法器的实现进行深入研究,提出了一种新的SIMD乘法器体系结构,采用两个16×8乘法器,通过对其操作数和结果进行符号扩展和拼接等处理,简单而高效地实现了16位FT-SIMD乘法器。同时,本体系结构可以扩展为32位和64位的SIMD乘法器。     

数据采集中的电压测量方法

本文介绍通信网监控系统中实现数据采集的电压测量方法。分析了二极管组成的有效值测量电路，提出了由乘法器及软件实现的有效值测量方法，指出用乘法器组成的电压有效值测量方法是成本低、精度高的最好方法。     

一种高性能乘法器生成器的设计

全新的基于全定制传输门结构42压缩高性能乘法生成器能根据用户输入自动产生并行乘法器的Verilog代码，并对Wallace Tree的连线进行了优化。最后在末级加法器阶段，生成器能根据到达的时延不同自动选择不同加法器最优的分段。在设计某些乘法器时生成器产生的代码综合结果在面积增加10％～20％左右时比Synopsys Design Ware库里相应的乘法器快5％-9％左右。     

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.     

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.     

全定制CORDIC运算器设计

浮点三角函数计算是导航系统、三维图像处理、雷达信号预处理等领域的基本运算.本文采用CORDIC算法及全定制集成电路设计方法实现了一种浮点三角函数计算电路,其输出数据兼容IEEE-754单精度浮点数标准.本文首先介绍了CORDIC算法的原理,并根据性能优先的原则采用了流水线结构;然后给出了基于SMIC O.13μm 1P...     

Comparative study of FFA architectures using different multiplier and adder topologies

Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.

     

基于标准单元库扩展的快速乘法器设计

设计并实现17×17 bit带符号数字乘法器。为了提高乘法器的性能,采用改进的Booth编码算法、Wal-lace树型结构以及基于标准单元库扩展的设计方法。该方法使用逻辑功效模型分析乘法器的关键路径,通过构造驱动能力更为完备的单元以实现关键路径中每一级门功效相等,从而得到最短路径延时。将TSMC 90 nm标准单元库扩展得到扩展单元库,使用两个单元库版图分别实现数字乘法器,基于扩展单元库实现的乘法器速度提升10.87%。实验结果表明,基于标准单元库扩展的半定制设计方法可以有效提升电路的性能,这种方法尤其适用于电路负载过大的情况。     

基于局部搜索与混合多样性策略的多目标粒子群算法

为了提高算法的收敛性与非支配解集的多样性,提出一种基于局部搜索与混合多样性策略的多目标粒子群算法（LH-MOPSO）.该算法使用增广Lagrange乘子法对非支配解进行局部搜索以快速接近Pareto最优解;利用基于改进的Maximin适应值函数与拥挤距离的混合多样性策略对非支配解集进行维护以保留解的多样性,同时引入高斯变异算子以避免算法早熟收敛;最后针对多目标约束优化问题,给出一种有效的约束处理方法.实验研究表明该算法具有良好的优化性能.     

一种多功能阵列乘法器的设计方法

为了实现不同数制的乘法共享硬件资源，提出了一种可以实现基于IEEE754标准的64位双精度浮点与32位单精度浮点、32位整数和16位定点的多功能阵列乘法器的设计方法。采用超前进位加法和流水线技术实现乘法器性能的提高。设计了与TMS320C6701乘法指令兼容的乘法单元，仿真结果验证了设计方案的正确性。     

An Optimized Deep-Learning-Based Low Power Approximate Multiplier Design

Approximate computing is a popular field for low power consumption that is used in several applications like image processing, video processing, multimedia and data mining. This Approximate computing is majorly performed with an arithmetic circuit particular with a multiplier. The multiplier is the most essential element used for approximate computing where the power consumption is majorly based on its performance. There are several researchers are worked on the approximate multiplier for power reduction for a few decades, but the design of low power approximate multiplier is not so easy. This seems a bigger challenge for digital industries to design an approximate multiplier with low power and minimum error rate with higher accuracy. To overcome these issues, the digital circuits are applied to the Deep Learning (DL) approaches for higher accuracy. In recent times, DL is the method that is used for higher learning and prediction accuracy in several fields. Therefore, the Long Short-Term Memory (LSTM) is a popular time series DL method is used in this work for approximate computing. To provide an optimal solution, the LSTM is combined with a meta-heuristics Jellyfish search optimisation technique to design an input aware deep learning-based approximate multiplier (DLAM). In this work, the jelly optimised LSTM model is used to enhance the error metrics performance of the Approximate multiplier. The optimal hyperparameters of the LSTM model are identified by jelly search optimisation. This fine-tuning is used to obtain an optimal solution to perform an LSTM with higher accuracy. The proposed pre-trained LSTM model is used to generate approximate design libraries for the different truncation levels as a function of area, delay, power and error metrics. The experimental results on an 8-bit multiplier with an image processing application shows that the proposed approximate computing multiplier achieved a superior area and power reduction with very good results on error rates.     

多特征融合的博客文章分类方法

博客已经成为了互联网上最热门的应用之一.博客文章内容千差万别,对其进行分类具有重要意义.博客文章有别于新闻文章,普通文本分类方法直接应用于博客文章效果不理想.提出一种新的方法,充分利用了博客文章特有的Tag、用户自定义类别等多个特征,并对各项特征进行融合.另外,通过对自定义类别进行预处理,过滤与类别无关的噪声单词.实验结果表明多特征融合的方法能够有效提高博客文章分类的准确率.