共查询到19条相似文献,搜索用时 93 毫秒
1.
2.
3.
4.
5.
在模拟电路演化领域,电路知识表示是首要解决的问题。网表编码操作简单,对于拓扑结构没有限制,但是网表编码会在种群初始化和遗传操作过程中产生大量的非法电路个体。为解决这一问题,提出结构矩阵,并总结出合法电路结构矩阵所具有的性质,以结构矩阵为规范设计出合适的种群初始化步骤和能够用于网表编码的结构交叉算子,通过演化来验证效果,实验结果显示该方法能够较好地解决网表编码所存在的问题。 相似文献
6.
7.
8.
基于演化算法的电路自动设计方法 总被引:3,自引:1,他引:3
在电路设计中引入演化计算,在可编程逻辑器件上通过对基本电路元器件进行演化而自动生成人工不可能设计出的电路结构,称为演化硬件设计。文中介绍了演化硬件实现的物质基础、演化计算在硬件自动设计方法的实现过程以及该方法要解决的问题,并对演化数字电路、模拟电路的设计进行了分析,说明演化算法在电路自动设计中是切实有效的。 相似文献
9.
10.
演化硬件的难点在于,当目标电路比较复杂时,解空间急骤增大,目前常用的演化方法及编码都存在一定的缺陷,可靠性不强。三元组编码是目前比较典型的一种方法,通过实验验证,在求解复杂问题时可靠性也不强,因此针对三元组编码提出一种改进策略,即利用树型结构对算法加以改进,提高算法可靠性,最终演化出消耗资源最少的数字电路.实验证明,算法改进是有效的,改进后的算法结果优于现有算法。 相似文献
11.
12.
针对高校微机继电保护课程,提出了一种基于TMS320F28335+EPM570F256C4+PC机的微机继电保护教学实验平台,以充分发挥DSP在数字信号处理及控制方面的优势,CPLD组合逻辑、译码及I/O扩展功能。详细介绍了平台的组成和保护装置接口电路的设计,其中包括DSP与CPLD接口电路、模拟量输入转换电路、开关量输入输出电路、测频电路以及人机接口电路。该平台配置相应模块化保护软件即可满足微机继电保护教学中,学生对装置硬件构成、数字算法、继电保护原理的感性理解和认识。 相似文献
13.
M.D. van de Burgwal K.C. Rovers K.C.H. Blom A.B.J. Kokkeler G.J.M. SmitAuthor vitae 《Microprocessors and Microsystems》2011,35(8):716-728
Traditionally, mechanically steered dishes or analog phased array beamforming systems have been used for radio frequency receivers, where strong directivity and high performance were much more important than low-cost requirements. Real-time controlled digital phased array beamforming could not be realized due to the high computational requirements and the implementation costs. Today, digital hardware has become powerful enough to perform the massive number of operations required for real-time digital beamforming. With the continuously decreasing price per transistor, high performance signal processing has become available by using multi-processor architectures. More and more applications are using beamforming to improve the spatial utilization of communication channels, resulting in many dedicated digital architectures for specific applications. By using a reconfigurable architecture, a single hardware platform can be used for different applications with different processing needs.In this article, we show how a reconfigurable multi-processor system-on-chip based architecture can be used for phased array processing, including an advanced tracking mechanism to continuously receive signals with a mobile satellite receiver. An adaptive beamformer for DVB-S satellite reception is presented that uses an Extended Constant Modulus Algorithm to track satellites. The receiver consists of 8 antennas and is mapped on three reconfigurable Montium TP processors. With a scenario based on a phased array antenna mounted on the roof of a car, we show that the adaptive steering algorithm is robust in dynamic scenarios and correctly demodulates the received signal. 相似文献
14.
本文主要对基于遗传算法的功能可重构数字体系进行了研究。首先对广泛用于算法级可重构电路设计中的遗传算法的基本思想作简要介绍,然后分析了现有的典型算法级功能可重构电路结构的特点,针对其中的不足,提出了一种基于遗传算法的自重构片上系统的设计方法。 相似文献
15.
面向多媒体的并行加速系统中可重构网络结构设计 总被引:1,自引:0,他引:1
本文讨论了面向多媒体数据处理的并行加速系统硬件平台的设计,采用数字信号处理芯片作为基本的工作单元,提出了一种基于mesh阵列的可重构网络结构设计及其控制方法,并对其性能进行了定性分析。 相似文献
16.
对于微小型无人直升机系统,本文介绍了基于DSP的三维测姿系统的硬件电路设计和四元数解算算法的实现及验证.该系统的硬件部分由角速率陀螺、滤波电路和DSP系统板等组成.角速率陀螺输出信号经过硬件滤波后由AD通道采集,经过数字滤波后,利用四元数算法解算出姿态数据.文中提出了硬件设计和实现及解算算法实现中需要注意的问题和相应的解决方案,测试结果表明该系统是有效的. 相似文献
17.
Seamus Cawley Fearghal Morgan Brian McGinley Sandeep Pande Liam McDaid Snaider Carrillo Jim Harkin 《Genetic Programming and Evolvable Machines》2011,12(3):257-280
EMBRACE has been proposed as a scalable, reconfigurable, mixed signal, embedded hardware Spiking Neural Network (SNN) device.
EMBRACE, which is yet to be realised, targets the issues of area, power and scalability through the use of a low area, low
power analogue neuron/synapse cell, and a digital packet-based Network on Chip (NoC) communication architecture. The paper
describes the implementation and testing of EMBRACE-FPGA, an FPGA-based hardware SNN prototype. The operation of the NoC inter-neuron
communication approach and its ability to support large scale, reconfigurable, highly interconnected SNNs is illustrated.
The paper describes an integrated training and configuration platform and an on-chip fitness function, which supports GA-based
evolution of SNN parameters. The practicalities of using the SNN development platform and SNN configuration toolset are described.
The paper considers the impact of latency jitter noise introduced by the NoC router and the EMBRACE-FPGA processor-based neuron/synapse
model on SNN accuracy and evolution time. Benchmark SNN applications are described and results demonstrate the evolution of
high quality and robust solutions in the presence of noise. The reconfigurable EMBRACE architecture enables future investigation
of adaptive hardware applications and self repair in evolvable hardware. 相似文献
18.
19.
针对语音识别系统对抗环境噪声的实际需求,提出一种二次组合抗噪技术,研究并设计了一种以数字信号处理器(DSP)为硬件平台,以隐马尔可夫模型(HMM)为算法的抗噪声嵌入式语音识别系统.DSP采用型号为TMS320VC5509A的芯片,配以外围硬件电路构成语音识别系统的硬件平台.软件设计以离散隐马尔可夫模型(DHMM)为识别算法进行编程,系统软件主要有识别、训练、学习和USB四个主要模块.实验结果表明:基于二次组合去噪技术的语音识别系统有更好的抗噪声效果. 相似文献