高性能低存储的2维离散小波变换架构

针对JPEG2000中的5/3小波和9/7小波存在的高存储问题,通过改进离散小波变换(DWT)的提升算法,提出了一种统一的高性能、低存储的2维离散小波变换架构.采用该算法实现的2维离散小波变换架构不仅省去了行列模块间的转置缓存,而且减小了片内缓存的大小.对于N×N大小的图像(N为图像宽度)进行5/32维DWT仅需要2N大小的片内缓存,进行9/7 2维DWT仅需要4N大小的片内缓存,而且通过采用流水线技术还可将关键路径缩短为一个乘法器的延时.和已有的2维DWT架构相比,该统一架构具有更低的片内存储器需求和更高的性能.该架构经Verilog HDL描述,并在ModelSim中验证正确.在Ahera Stratix Ⅱ FPGA EP2S60F1024C4中综合的结果显示,对于1 024×1 024大小的图像,需要1 284个ALUT,片内存储器的大小为4 K,最高频率可达172.56 MHz.     

二维翻转结构9/7离散小波逆变换研究与VLSI实现

采用提升结构的二维9/7离散小波逆变换模块是高清图像解码显示和实时处理的关键支撑技术。为实现电路模块的整体优化,在提升结构二维9/7离散小波逆变换标准算法的研究基础上,通过分析图像数据的输入输出顺序,结合器件模型提出一种翻转结构的优化算法。进一步地,给出了所提算法的一种多核并行VLSI结构：通过流水线技术将关键路径降为一级乘法器延迟;通过重组织数据流,处理N×N大小的图像仅需4N的中间缓存,从而在提升该模块速率的同时降低了中间缓存。基于Sparten6-xc6slx150t FPGA进行综合验证,结果表明该模块可稳定运行于166.34 MHz时钟速率。     

航天器图像压缩小波变换的FPGA设计

为了实现基于FPGA的CCSDS图像压缩算法,在提升小波变换结构的基础上,提出了一种改进的基于行的并行3级2-D整数9/7小波变换实现结构.结构充分利用流水线设计技术,对于每一级2-D DWT,结构包含2个行处理器同时处理2行数据,借助10个行缓存存储变换的中间数据,实现了行、列变换的并行运算.同时对于3级小波变换,也采用了流水线结构,减少了存储器的使用量和对其访问造成的时间延迟,提高了变换速度.本结构完成分辨率为N×N灰度图像的3级小波分解所用的时钟周期约为O(N2/ 2).采用Altera的Stratix II FPGA实验,结果表明,本整数小波变换结构具有较高的吞吐率和变换速度,可以工作在86.5MHz的频率下,实现1024×1024灰度图像100fps的图像实时变换.     

传感器网络中图像小波处理的低存储硬件实现

为了适应当前传感器网络中越来越多的图像压缩处理,提出了一种片上低存储离散小波变换(DWT)的超大规模集成电路(VLSI)结构.现今人们周围遍布各种图像采集设备,包括监视器、电脑、手机视频摄像头等,并且人们对图像精度的需求越来越高,使得传统软件处理图像压缩的速度逐渐无法满足人们的需求,这就需要考虑使用硬件处理来进行加速.小波变换常被用于图像的压缩,而采用5/3提升小波技术来进行硬件实现相对比较方便.为减少硬件的片上存储,通过特殊的调度运算方式进行行列并行运算有效降低片上存储需求.该设计进行RTL级仿真并使用SMIC的0.18μm工艺进行综合,结果表明:该调度方法可以大大节省缓存单元,并且在100 MHz时钟下就可以保证对高清图像的快速处理,可以满足当前传感器网络中图像压缩解码的需求.     

基于翻转结构的离散小波变换片上系统设计验证

论文研究了二维提升结构9／7小波变换模块电路实现;通过分析小波变换过程中数据流格式及输入输出规律,指出可基于片上系统软硬件协同地完成小波变换;据此设计了基于翻转结构的一维小波变换专用处理电路用于水平方向一维小波变换;通过嵌入式软核读取中间结果,用于垂直方向一维小波变换。对标准图像的测试结果表明：平均仅需4ms-5ms时间即可完成512×512大小图像的9／7小波变换,具有较高的工程实用价值。     

一种用于JPEG2000的小波变换VLSI结构设计方法

为了快速地进行小波变换,提出了一种应用于JPEG2000的基于提升格式5/3,9/7统一的离散小波滤波单元;同时对于行列并行滤波,提出了一种控制机制,其在缓存5行的条件下,可完成高速行列并行滤波操作。该方法在保证精度条件下,可以取得较高的硬件利用率,且中间数据暂存空间需求低。然后在提升结构基础上,完成了硬件模块设计,并进行了仿真和FPGA实现。最后用Verilog HDL对系统进行了硬件描述,并在Altera DE2的验证板上的cyclone2 EP2C35FC672芯片上,在Quartus 6.0环境下实现了该结构功能。     

基于FPGA的二维DCT IP核优化设计

采用行列分解法实现了二维DCT变换,其一维DCT采用Loeffler算法结构,结合位宽优化与CSD乘法优化,在FPGA芯片上无内嵌硬件乘法器情况下,一维DCT计算模块仅需要1504LUTs;有内嵌硬件乘法器情况下,仅需要688LUTs与22个内嵌9*9乘法器。将二维DCT计算模块封装为wishbone接口的IP核,在AlteraDE2-70开发板上实测二维DCT计算速度是软件快速DCT算法的296倍,可应用于JPEG图像处理、音频处理等场合。     

二维离散小波提升变换算法的并行结构设计

提出了一种二维离散小波提升变换（2DDWT）的2×2并行结构。该结构充分利用了2DDWT算法固有的行并行、列并行、行列并行的三种并行性,有效提高了算法执行速度,同时显著降低了硬件存储需求。处理N×N图像的时间为N2/4+N/2+1,系统存储需求为3N。FPGA实现结果证明了本设计的正确性和有效性。     

一种基于Loeffler算法的快速实现2D DCT/IDCT的方法*

提出了一种基于Loeffler[8]算法的快速实现二维离散余弦变换/反离散余弦变换（2D DCT/IDCT）的方法。采用行列分解的方式,仅使用一个1D DCT/IDCT处理核快速完成8×8的2D DCT/IDCT变换。通过合理安排时钟周期数和简化各周期内的操作,使1D DCT/IDCT模块能在八个时钟周期内快速完成一次变换。仿真试验表明,与目前使用相同FPGA芯片的商业IP核相比,所使用的资源减少了10％,而速度却提高了10％。     

Xeon Phi平台上基于模板优化的3D-GVF场计算加速

3D梯度向量流场（3D GVF field）广泛应用于多种3D图像分析算法中,其计算需要多次迭代,计算量大,如何提高其计算速度具有重要的研究意义。面向Intel Xeon Phi众核集成架构,首次进行了3D GVF场计算的加速优化。首先,挖掘3D图像像素点间存在的天然并行性,发挥众核架构优势,尝试线程级并行（多核）和数据级并行（SIMD）。其次,3D GVF场的计算过程是一种典型的3D 7点模板运算,结合Xeon Phi架构的L2 缓存规格,提出一种高效的数据分块策略,充分挖掘数据的时/空局部性,有效缓解模板计算引起的缓存缺失,提升了计算性能。实验结果表明,引入模板优化技术能显著提升3D GVF场的计算速度,在图像维度为5123时,所提方法在57核Xeon Phi平台上的性能相比在2.6GHz 8核16线程的Intel Xeon E5 2670 CPU上的性能,加速比可达2.77。     

A Novel VLSI Architecture for Real-Time Line-Based Wavelet Transform Using Lifting Scheme

In this paper, we propose a VLSI architecture that performs the line-based discrete wavelet transform （DWT） using a lifting scheme. The architecture consists of row processors, column processors, an intermediate buffer and a control module. Row processor and Column processor work as the horizontal and vertical filters respectively. Intermediate buffer is composed of five FIFOs to store temporary results of horizontal filter. Control module schedules the output order to external memory. Compared with existing ones, the presented architecture parallelizes all levels of wavelet transform to compute multilevel DWT within one image transmission time, and uses no external but one intermediate buffer to store several line results of horizontal filtering, which decreases resource required significantly and reduces memory efficiently. This architecture is suitable for various real-time image/video applications.     

高性能二维9/7离散小波变换VLSI结构

为了降低二维小波变换中的存储消耗并同时提高电路处理速度,提出了一种二维并行的VLSI结构。通过充分挖掘二维变换中行变换和列变换之间的关系,优化了行变换核和列变换核的并行数据扫描输入方式,将9/7小波变换的中间存储降低至4N。同时,采用基于翻转格式的流水线技术,将电路的关键路径缩短至一级乘法器延时,有效地提高了电路处理速度,并通过伸缩电路合并的优化方法将乘法器个数降低至10个,从而有效地减少了硬件资源消耗。     

低功耗并行的二维离散小波变换的VLSI结构

提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理,不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块,该结构同时可以对两行数据进行处理,硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现,大大降低了需要的片上存储器的数量以及对片外存储器的访问,有效地降低了系统的功耗。     

Parallel multi‐level 2D‐DWT on CUDA GPUs and its application in ring artifact removal

This paper presented two schemes of parallel 2D discrete wavelet transform (DWT) on Compute Unified Device Architecture graphics processing units. For the first scheme, the image and filter are transformed to spectral domain by using Fast Fourier Transformation (FFT), multiplied and then transformed back to space domain by using inverse FFT. For the second scheme, the image pixels are convolved directly with filters. Because there is no data relevance, the convolution for data points on different positions could be executed concurrently. To reduce data transfer, the boundary extension and down‐sampling are processed during data loading stage, and transposing is completed implicitly during data storage. A similar skill is adopted when parallelizing inverse 2D DWT. To further speed up the data access, the filter coefficients are stored in the constant memory. We have parallelized the 2D DWT for dozens of wavelet types and achieved a speedup factor of over 380 times compared with that of its CPU version. We applied the parallel 2D DWT in a ring artifact removal procedure; the executing speed was accelerated near 200 times compared with its CPU version. The experimental results showed that the proposed parallel 2D DWT on graphics processing units can significantly improve the performance for a wide variety of wavelet types and is promising for various applications. Copyright © 2015 John Wiley & Sons, Ltd.     

提升小波变换的三种算法性能比较

离散小波变换(DWT)在语音,图像等信号处理中有着广泛的应用,在JPEG2000标准中就推荐采用5/3和9/7小波来分别进行无损和有损图像压缩,取代基于DCT变换的图像压缩,并且还推荐采用提升方法来实现。提出三种基于提升方法的二维离散小波变换的并行算法,并在超常超标量数字指令(VLIW)的数字信号处理器(DSP)上进行了性能方面的比较。这里,我们以在图像压缩中常用的不同分辨率的图像作为实验对象。实验结果表明,此三种算法对图像数据进行小波变换的处理时间有了明显缩短,并且实现在参数空间的不同点上都得到更好的效果。     

High-performance processor design based on 3D on-chip cache

Interconnection becomes one of main concerns in current and future microprocessor designs from both performance and consumption. Three-dimensional integration technology, with its capability to shorten the wire length, is a promising method to mitigate the interconnection related issues. In this paper we implement a novel high-performance processor architecture based 3D on-chip cache to show the potential performance and power benefits achievable through 3D integration technology. We separate other logic module and cache module and stack 3D cache with the processor which reduces the global interconnection, power consumption and improves access speed. The performance of 3D processor and 3D cache at different node is simulated using 3D Cacti tools and theoretical algorithms. The results show that comparing with 2D, power consumption of the storage system is reduced by about 50%, access time and cycle time of the processor increase 18.57% and 21.41%, respectively. The reduced percentage of the critical path delay is up to 81.17%.     

5/3小波提升结构的深度流水线优化*

为了满足基于小波变换的高速信号实时处理的需求,在FPGA上实现更高速的5/3小波变换。采用静态时序分析的方法分析了当前5/3小波变换结构中影响速度的主要因素,并采用深度流水线技术切断原结构中存在的较长组合逻辑路径,从而提高了最高工作频率。使设计中仅增加少量寄存器开销便可获得原结构250％的速度,最高可实现每秒300M样本的数据吞吐量,可用于设计基于小波变换和FPGA的高速信号处理系统。     

VLSI Implementation of Discrete Wavelet Transform for Lossless Compression of Medical Images

This paper presents a VLSI architecture to implement the forward and inverse two dimensional Discrete Wavelet Transform (DWT), to compress medical images for storage and retrieval. Lossless compression is usually required in the medical image field. The word length required for lossless compression makes too expensive the area cost of the architectures that appear in the literature. Thus, there is a clear need for designing a cost-effective architecture to implement the lossless compression of medical images using DWT. The data path word length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area. The pyramid algorithm is reorganized and the algorithm locality is improved in order to obtain an efficient hardware implementation. The result is a pipelined architecture that supports single chip implementation in VLSI technology. The implementation employs only one multiplier and 352 memory elements to compute all scales what results in a considerable smaller chip area (45 mm²) than former implementations. The hardware design has been captured by means of the VHDL language and simulated on data taken from random images. Implemented in a 0.7 μm technology, it can compute both the forward and inverse DWT at a rate of 3.5 512×512 12 bit images/s corresponding to a clock speed of 33 MHz. This chip is the core of a PCI board that will speedup the DWT computation on desktop computers.     

小波滤波器低功耗并行的VLSI结构设计

提出一种基于行和提升算法,实现JPEG2000编码系统中的小波正反变换(discretewavelettransform)的低功耗、并行的VLSI结构设计方法·利用该方法所得结构一次处理两行数据,分时复用行处理器,使行处理器内以及行、列处理器实现并行处理,且最小化行缓存·对称扩展通过嵌入式电路实现,整个结构采用流水线设计方法优化,加快了变换速度,增加了硬件资源利用率,降低了功耗,效率几乎达到100%·小波滤波器正反变换结构已经经过FPGA验证,可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中·