路由芯片中的微流水设计

微流水技术是异步电路中实现流水线设计的有效方法，而路由芯片是高速通信网络中的重要硬件部件。文中首先介绍了微流水设计的基本结构和控制，然后介绍了采用 洞机制的路由芯片的工作机理，并给出了利用微流水实现ＡＳＩＣ路由芯片的具体应用，该芯片达到了简单、高效、可靠的设计目标，文中的最后还给出了在线较复杂的电路系统中实现微流水所需要进一步研究的问题。     

模块化路由软件实现技术分析与研究

本文针对目前互联网上存在的三套独立的开源模块化路由软件：MRT、GateD、GNU Zebra,从其软件体系结构及单个路由协议实现技术方面做了全面的总结和比较。为我们设计路由软件提供了很好的启示。     

Trie树路由查找算法在网络处理器中的实现

Trie树数据结构的实现方法灵活,所需存储器空间小,是实现高速路由查找和分组转发的理想选择。为满足10 Gb/s线速度网络处理器中微引擎的设计要求,提出一种基于最优平衡、多层存储的Trie树路由查找算法。建立一种平衡的压缩树结构,将该树中相邻的多层节点压缩到一个存储节点中。通过构造特定的数据存储结构来减小树的搜索深度,以空间换取时间,从而提高路由查找速度和分组转发效率。在网络处理器的查找微引擎设计中实现Trie路由查找算法,实验结果表明,单个微引擎的查找速度为4.4 Mb/s,能达到节省存储空间、提高查找效率的效果。     

片上网络芯片——完美解决由路由拥塞引起的互联成本上涨问题

随着有线路由的纳米化发展,网络互联设计已成为制作系统芯片(SoC)的一个重要的考虑因素.而系统芯片进行IP互联所引起的导线消耗成为了芯片发展的制约因素.另一方面,路由的拥塞也间接地限制了系统芯片平面布局的紧凑性.因此芯片设计供应商已投入大量资金来研发物理综合工具,优化系统芯片,用于改善芯片布局和减少网络互联环节导线的使用量.此外,片上网络芯片(NoC)的研发也以最大限度地减少导线使用量作为设计的第一考虑因素.     

模块化路由软件实现技术分析与研究

本文针对目前互联网上存在的三套独立的开源模块化路由软件:MRT、GateD、GNU Zebra,从其软件体系结构及单个路由协议实现技术方面做了全面的总结和比较。为我们设计路由软件提供了很好的启示。     

基于规则引擎的无线传感器网络动态路由系统

无线传感器网络路由协议往往是针对特定的任务类型和网络状态设计的,动态路由系统可以在运行时,自适应地选择性能最优的路由协议.利用规则引擎设计了一种无线传感器网络动态路由系统.采用了模块化的设计方法,使得多路由协议共存时可以共享资源.利用规则引擎的灵活性和智能性实现路由协议的自适应切换机制.实验结果显示,在多任务网络环境下,动态路由在满足服务质量的同时可以有效地降低网络能耗.     

多层次域间路由安全监测系统的设计与实现

基于边界网关协议(BGP)的域间路由系统已经成为Internet的核心路由设施,但由于BGP本身缺乏安全机制,很容易受到各种人为配置错误或者恶意攻击的影响。我们开发的域间路由监测系统可以从4个层次实现对域间路由的安全监测,分别是Internet、国家网络、特定ISP和特定路由。本文详细介绍了多层次域间路由安全监测系统的组成结构、软件结构、设计思想、实现技术和测试结果。     

NoC节点编码及路由算法的研究

NoC的设计和实现受到芯片的面积、功耗、深亚微米效应的限制.将拓扑结构和节点编码相结合,提出一种基于约翰逊码的二维平面编码.该编码隐含了Torus网络拓扑结构以及网络节点之间的连接关系并且有很好的扩展性,能够简化Torus拓扑结构上路由算法的实现和降低硬件成本.基于此编码和利用X-Y路由的路由确定性特点,提出改进X-Y路由,在中间节点只需要3或5个逻辑运算,降低路由的计算复杂性和硬件成本.最后,进行了节点结构设计.提出的编码不仅用于NoC的路由方面而且在NoC任务映射方面有重要应用.     

基于骨干网的数据中心网络服务规划设计

数据中心是云计算的核心,而当前基于电交换器、传统多级交换网络、集中放置与管理的数据中心架构无法满足未来云服务对高性能数据中心在可生存性、高可用性与设计灵活性等方面的要求。以网络可生存性和最小化网络代价为目标,针对数据中心的放置、服务路由及保护进行联合优化设计。首先通过设计ILP获取最优解。该ILP集成了p-cycle、服务量备份以及快速重路由等思想,分别针对单个链路或单个服务器损坏进行快速保护。然后进一步给出一种启发式算法,该算法包含数据中心的放置及服务路由和快速保护两大步骤。ILP和启发式两种方法最终都通过广泛的仿真实验进行了验证。     

LR-WPAN捷径式能量均衡树路由算法研究

针对LR-WPAN网络中ZigBee树路由算法存在的不足,在综合考虑单个节点的生存周期和整个网络能量消耗的基础上,提出一种捷径式能量均衡树路由算法。通过在节点中使用邻居表以及表中添加动态剩余能量标志位,结合路由跳数、节点和网络的能量状态设计路由算法。运用仿真实验与原始树路由算法进行分析对比,表明改进后的路由算法有效地降低了路由开销和网络节点间的延时,提高了节点存活率和路由效率,达到优化网络能效,延长网络生存周期的目的。     

Obtaining the optimal configuration of high-radix Combined switches

High-radix switches reduce network cost and improve network performance, especially in large switch-based interconnection networks. However, there are some problems related to the integration scale to implement such switches in a single chip. An interesting alternative for building high-radix switches consists of combining several current smaller single-chip switches to obtain switches with a greater number of ports. A key design issue of this kind of high-radix switches is the internal switch configuration, specifically, the correspondence between the ports of these high-radix switches and the ports of their smaller internal single-chip switches. In this paper we use artificial intelligence and data mining techniques in order to obtain the optimal internal configuration of all the switches in the network of large supercomputers running parallel applications. Simulation results show that using the resultant switch configurations, it is possible to achieve similar performance as with single-chip switches with the same radix, which would be unfeasible with the current integration scale.     

高阶路由器结构研究综述

随着高性能网络规模的增加,高阶路由器结构设计成为高性能计算中研究的重点和热点。使用高阶路由器,网络能实现更低的报文传输延迟、网络构建成本和网络功耗,同时高阶路由器的应用还可以提高网络可靠性。过去十年是高阶路由器发展最快的时期,对近年高阶路由器的研究进行了综述,并对未来发展趋势进行了预测,主要介绍了以YARC为代表的经典结构化设计以及"network within a network"等近年来涌现的新型设计方法。未来的研究重点是解决高阶路由器结构设计中遇到的缓存和仲裁等各种问题,并利用光互连等技术设计性能更好的结构。     

片上网络中低延时可扩展的路由器结构设计

为了满足片上网络中路由器能同时支持多个IP核的要求,并同时具有较好的延时性能,设计了一种分布式路由和仲裁的路由器结构。其中的仲裁模块根据当前路由器各输入端口的请求状态和下一路由器相应输入端口缓冲器的状态进行仲裁,此仲裁方法提高了数据包传输的成功率,从而降低了传输延时,使路由器具有良好的延时性能,同时仿真结果表明:该路由器在面积开销方面具有良好的可扩展性。     

Cost-Efficient Dragonfly Topology for Large-Scale Systems

It is more efficient to use increasing pin bandwidth by creating high-radix routers with a large number of narrow ports instead of low-radix routers with fewer wide ports. Building networks using high-radix routers lowers cost and improves performance, but also presents many challenges. The dragonfly topology minimizes network cost by reducing the number of global channels required.     

Design and performance of speculative flow control for high-radix datacenter interconnect switches

High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and low cost than low-radix switches [J. Kim, W.J. Dally, B. Towles, A.K. Gupta, Microarchitecture of a high-radix router, in: Proc. ISCA 2005, Madison, WI, 2005]. Unfortunately, most existing switch architectures do not scale well to a large number of ports, for example, the complexity of the buffered crossbar architecture scales quadratically with the number of ports. Compounded with support for long round-trip times and many virtual channels, the overall buffer requirements limit the feasibility of such switches to modest port counts. Compromising on the buffer sizing leads to a drastic increase in latency and reduction in throughput, as long as traditional credit flow control is employed at the link level. We propose a novel link-level flow control protocol that enables high-performance scalable switches that are based on the increasingly popular buffered crossbar architecture, to scale to higher port counts without sacrificing performance. By combining credited and speculative transmission, this scheme achieves reliable delivery, low latency, and high throughput, even with crosspoint buffers that are significantly smaller than the round-trip time. The proposed scheme substantially reduces message latency and improves throughput of partially buffered crossbar switches loaded with synthetic uniform and non-uniform bursty traffic. Moreover, simulations replaying traces of several typical MPI applications demonstrate communication speedup factors of 2 to 10 times.     

VLSI中高性能X结构多层总体布线器

X结构带来物理设计诸多性能的提高,该结构的引入和多层工艺的普及,使得总体布线算法更复杂.为此,在XGRouter布线器的基础上,本文设计了三种有效的加强策略,包括:1)增加新类型的布线方式;2)粒子群优化(Particle swarm optimization,PSO)算法与基于新布线代价的迷宫布线的结合;3)初始阶段中预布线容量的缩减策略,继而引入了多层布线模型,简化了XGRouter的整数线性规划模型,最终构建了一种高性能的X结构多层总体布线器,称为ML-XGRouter.在标准测试电路的仿真实验结果表明,ML-XGRouter相对其他各类总体布线器,在多层总体布线中最重要的优化目标|溢出数和线长总代价两个指标上均取得最佳.     

A Yield-Driven Gridless Router

A new gridless router to improve the yield of IC layout is presented. The improvement of yield is achieved by reducing the critical areas where the circuit failures are likely to happen. This gridless area router benefits from a novel cost function to compute critical areas during routing process, and heuristically lays the patterns on the chip area where it is less possible to induce critical area. The router also takes other objectives into consideration, such as routing completion rate and nets length. It takes advantage of gridless routing to gain more flexibility and a higher completion rate. The experimental results show that critical areas are effectively decreased by 21% on average while maintaining the routing completion rate over 99%.     

一种基于马尔可夫模型的加速ICN路径收敛性的方法

在新型的内容中心网络(Information-Centric Networking, ICN)多宿主场景中,主机的标识和地址分离,允许数据包中携带多个地址。多目的地址的数据包在匹配路由表之后获得多个转发端口,在每跳具有路径选择的能力,可以根据网络的动态进行路径调整。然而,这种转发方法打破了根据路由表最短路径转发规则,数据包可能在网络中来回跳动而不能尽快收敛到目的地。本文提出一种基于马尔可夫模型的多地址裁剪方法,该模型能根据历史地址裁剪状态信息进行裁剪决策,从而提高路径的收敛性。实验结果表明该方法与基准方法相比,在保证传输速率几乎相同的同时,平均跳数减少约16%,在路径收敛性方面得到了改善。     

A practical low-latency router architecture with wing channel for on-chip network

With increasing number of cores, the communication latency of Network-on-Chip becomes a dominant problem due to complex operations per node. In this paper, we try to reduce communication latency by proposing single-cycle router architecture with wing channel, which forwards the incoming packets to free ports immediately with the inspection of switch allocation results. Also, the incoming packets granted with wing channel can fill in the time-slots of crossbar switch and reduce the contentions with subsequent ones, thereby pushing throughput effectively. We design the proposed router using 65 nm CMOS process, and the results show that it supports different routing schemes and outperforms express virtual channel, prediction and Kumar’s single-cycle ones in terms of latency and throughput. When compared to the speculative router, it provides 45.7% latency reduction and 14.0% throughput improvement. Moreover, we show that the proposed design incurs a modest area overhead of 8.1% but the power consumption is saved by 7.8% due to less arbitration activities.     

Formalization and configuration methodology for high-radix combined switches

In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency since hop count is also reduced. However, there are some difficulties related to integration scale to design such switches. In this paper we present and formalize an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller switches to obtain switches having greater number of ports. This strategy will remain valid as the scale of integration keeps evolving. Although simple, this strategy raises key design challenges in order to these high-radix switches achieve the best performance. The resultant internal structure of these switches becomes an important design decision, and an arbitrary selection may produce a significant performance degradation. For this reason, we also propose a general methodology to configure in an optimal way the internal switch structure and apply it to a particular case in order to show how it works. The resultant switch configurations are evaluated in order to show the real potential of our proposal.