紧凑的Aigis-sig数字签名方案软硬件协同实现方法

基于理想格构造的 Aigis-sig 数字签名方案具有实现效率高、签名长度短、抗量子攻击等优势。针对Aigis-sig方案,构造了一种改进的模乘计算元件,设计了一种基于快速数论变换（NTT）算法实现环上多项式运算的紧凑硬件架构;同时以此架构为基础,提出了Aigis-sig数字签名方案的FPGA软硬件协同实现方法。实验表明,在Xilinx Zynq-7000 SoC平台上,CPU频率和硬件频率分别设置为666.66 MHz和150 MHz时,该实现方案相较于纯软件实现,签名阶段和验签阶段分别取得约26%和17%的性能提升。     

基于IB-IWT实时图像压缩的FPGA设计与实现

针对内插双正交整数小波变换（IB-IWT）的实时图像压缩特点,提出了一种FPGA设计方案．首先通过分析IB-IWT算法的特点,给出了适合硬件实现的实时图像压缩方案．然后选取高端FPGA作为硬件处理平台,对图像压缩的小波变换、小波系数编码及其小波变换的边界处理和有限字长效应等关键技术进行了研究,提出了适合于FPGA的53小波变换的快速实现方法及其小波系数的编码方法．最后,利用FPGA对图像进行了压缩．该设计方案整合标志位图思想和并行SPIHT算法结构的优势,充分利用了FPGA内部的丰富资源．实验结果表明,该方案以其低计算复杂度、低内存需求量和高实时处理速度等特点成为实时压缩算法硬件实现的优选方案．     

一种基于FPGA的直扩系统快速捕获算法

本文提出一种基于FPGA的频域相关的捕获算法。该算法利用快速傅里叶变换(FFT)实现伪码的快速相关,同时利用离散傅里叶变换频移定理,补偿多普勒频偏,实现大多普勒频偏下的快速捕获。仿真以FPGA实现测试表明,该算法在模拟快速移动载体通信环境下,捕获时间小于40ms,漏警概率小于3×10-3,虚警概率小于3×10-6。     

计算一类数字变换的收缩阵列

本文以DFT的收缩(Systolic)阵列结构为基础,给出了一类数字变换在这种结构上的VLSI并行实现,这些变换包括离散富里叶变换,离散余弦变换,离散正弦变换,离散Hartley变换,数论变换和多项式变换。这些基本的阵列结构是构造大规模收缩阵列的基础。     

数论FNT计算机

本文讨论数论变换中的RNS算术运算、最有用的Fermat数变换及其VLSI的实现。     

一种面向FPGA的快速Hough变换

在FPGA上设计并实现了一种用于直线检测的快速Hough变换方法。使用分类滤波器把直线目标分成多个方向,使多个方向上的运算在空间上实现了并行处理;在每个方向上,设计实现了一种用于Hough变换的流水线处理结构;提出了一种基于直方图统计的两阶段搜索算法。大量的实验验证了提出的Hough变换实现方法的可行性,结果证明该方法占用空间少,实时性高。     

利用对称性加速实序列FFT的方法及其FPGA实现*

针对工程实践中傅里叶变换的输入序列一般为实序列的情况,充分利用FFT（快速傅里叶变换）奇偶虚实的对称性质,提出了一种实序列FFT的加速算法。将2N点的实序列DFT转换为N点的复序列DFT,并行计算使运算量明显减少;并给出了基于FPGA的硬件实现方法。     

数论变换的实算及其硬化的探讨

数论变换是进行快速褶积的有力手段,是在深入研究富氏变换结构和性质的基础上,运用数论的概念于七十年代初产生的。数论变换在整数环中进行运算,避免了富氏变换中复数运算的合入误差,而且,它用移位代替了富氏变换中的复数乘法,大大提高了在计算机上进     

基于FPGA和DSP的印刷品数字水印检测器的设计

采用高端CMOS图像传感器进行图像采集,基于DCT和M序列算法实现数字水印提取,基于FPGA采用DA算法实现二维DCT变换。与基于PC机和扫描仪的印刷品数字水印检测设备相比,大大提高了图片数字水印检测的速度,实现了印刷品数字水印的快速检测。     

基于FPGA的静态实时光谱采集与处理系统

为了实时获取静态迈克尔逊干涉仪得到的光谱信息,设计了基于FPGA的实时光谱采集分析系统。在Xilinx FPGA芯片上实现了干涉条纹到光谱数据的实时处理。在算法处理过程中,实现了干涉条纹滤波去噪、快速傅里叶变换、相位标定、光谱数据传输等模块化功能。实验结果显示,系统可以高速采集并实时处理光谱数据。     

NTT--数论变换算法在图像压缩技术中的应用研究

提出了一种全新的图像数据压缩算法,即数论变换（Ｎｕｍｂｅｒ Ｔｈｅｏｒｙ Ｔｒａｎｓｆｏｒｍａｔｉｏｎ,ＮＴＴ）算法,证明了在以正整数ｐ为模的整数环Ｚｐ上ＮＴＴ是线性正交变换,以及在Ｚｐ上具有卷积特性等,设计了具有ＦＦＴ类型的快速算法,该算法可采用移位操作实现,其程度优于ＤＣＴ变换,最后通过实例比较,说明了该算法在图像数据压缩中表现出运算速度快、精度高和压缩效果好等优点,ＮＴＴ算法的研究,为图像压     

Advanced computational models and learning theories for spoken language processing

Recent developments in research on humanoid robots and interactive agents have highlighted the importance of and expectation on automatic speech recognition (ASR) as a means of endowing such an agent with the ability to communicate via speech. This article describes some of the approaches pursued at NTT Communication Science Laboratories (NTT-CSL) for dealing with such challenges in ASR. In particular, we focus on methods for fast search through finite-state machines, Bayesian solutions for modeling and classification of speech, and a discriminative training approach for minimizing errors in large vocabulary continuous speech recognition.     

采用FPGA的机器视觉系统发展现状与趋势

采用FPGA作为主要运算器件的嵌入式视觉系统具有高性能、低功耗、结构紧凑等特点,是计算机视觉的研究热点之一,有着广阔的应用前景。文章对近年来国内外基于FPGA的嵌入式视觉系统方面有代表性的研究成果进行了介绍,并对相关研究领域目前存在的主要问题以及发展趋势进行了讨论。     

FPGA implementation of a run-time configurable NTT-based polynomial multiplication hardware

Multiplication of polynomials of large degrees is the predominant operation in lattice-based cryptosystems in terms of execution time. This motivates the study of its fast and efficient implementations in hardware. Also, applications such as those using homomorphic encryption need to operate with polynomials of different parameter sets. This calls for design of configurable hardware architectures that can support multiplication of polynomials of various degrees and coefficient sizes.In this work, we present the design and an FPGA implementation of a run-time configurable and highly parallelized NTT-based polynomial multiplication architecture, which proves to be effective as an accelerator for lattice-based cryptosystems. The proposed polynomial multiplier can also be used to perform Number Theoretic Transform (NTT) and Inverse NTT (INTT) operations. It supports 6 different parameter sets, which are used in lattice-based homomorphic encryption and/or post-quantum cryptosystems. We also present a hardware/software co-design framework, which provides high-speed communication between the CPU and the FPGA connected by PCIe standard interface provided by the RIFFA driver [1]. For proof of concept, the proposed polynomial multiplier is deployed in this framework to accelerate the decryption operation of Brakerski/Fan-Vercauteren (BFV) homomorphic encryption scheme implemented in Simple Encrypted Arithmetic Library (SEAL), by the Cryptography Research Group at Microsoft Research [2]. In the proposed framework, polynomial multiplication operation in the decryption of the BFV scheme is offloaded to the accelerator in the FPGA via PCIe bus while the rest of operations in the decryption are executed in software running on an off-the-shelf desktop computer. The hardware part of the proposed framework targets Xilinx Virtex-7 FPGA device and the proposed framework achieves the speedup of almost 7 ×  in latency for the offloaded operations compared to their pure software implementations, excluding I/O overhead.     

CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on-chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in the literature are destined to System-on-chip (SoCs) designs. For a FPGA-based system, in order to take all benefits from this technology, the proposed NoCs are not suitable. In this paper, we present a new paradigm called CuNoC for intercommunication between modules dynamically placed on a chip for the FPGA-based reconfigurable devices. The CuNoC is based on a scalable communication unit characterized by unique architecture, arbitration policy base on the priority-to-the-right rule and modified XY adaptive routing algorithm. The CuNoC is namely adapted and suited to the FPGA-based reconfigurable devices but it can be also adapted with small modifications to all other systems which need an efficient communication medium. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main already proposed NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and implementation results are also given.     

从1394 VHDL代码移植看FPGA设计

通过从基于FPGA设计的1394物理层芯片与链路层芯片合并为一个FPGA芯片且由双端口升为三端口的VHDL代码移植过程，介绍1394芯片基本原理和移植中所产生的问题解决办法，阐述FPGA芯片设计的代码规范化的重要性以及一些基本技巧。     

FPGA implementation of particle swarm optimization for Bayesian network learning

Using a Bayesian network (BN) learned from data can aid in diagnosing and predicting failures within a system while achieving other capabilities such as the monitoring of a system. However, learning a BN requires computationally intensive processes. This makes BN learning a candidate for acceleration using reconfigurable hardware such as field-programmable gate arrays (FPGAs). We present a FPGA-based implementation of BN learning using particle-swarm optimization (PSO). This design thus occupies the intersection of three areas: reconfigurable computing, BN learning, and PSO. There is significant prior work in each of these three areas. Indeed, there are examples of prior work in each pair among the three. However, the present work is the first to study the combination of all three. As a baseline, we use a prior software implementation of BN learning using PSO. We compare this to our FPGA-based implementation to study trade-offs in terms of performance and cost. Both designs use a master–slave topology and floating-point calculations for the fitness function. The performance of the FPGA-based version is limited not by the fitness function, but rather by the construction of conditional probability tables (CPTs). The CPT construction only requires integer calculations. We exploit this difference by separating these two functions into separate clock domains. The FPGA-based solution achieves about 2.6 times the number of fitness evaluations per second per slave compared to the software implementation.     

Speech recognition and synthesis technology development at NTT for telecommunications services

This paper describes recent developments at NTT in the areas of speech recognition, speech synthesis, and interactive voice systems as they relate to telecommunications applications. Speaker-independent largevocabulary speech recognition based on context-dependent phone models and LR parser, and high-quality text-to-speech (TTS) conversion using the waveform concatenation method, both realized as software, have enabled interactive voice systems for fast and easy prototyping of telephone-based applications. Practical applications are discussed with examples.     

基于二维FFT的图像滤波方法及实现

二维快速傅立叶变换(FFT)在一个传统概念的处理机上实现时,需要芯片具有更多的逻辑资源。本文给出了基于FPGA的自定义处理机(CCM)的二维FFT算法和实现。在CCM的Splash-2平台上实现了二维FFT,计算速度达到180Mflops,最快速度超过Sparc-10工作站的23倍。同时,对于一个N×N图像,这种实现方法可以满足二维FFT所需要的O(N2log2N)次的浮点算术运算。     

数字通信系统中的符号时钟恢复技术

在数字通信系统中,由于有高斯噪声和多径的影响,接收信号产生损失,从而导致时钟信号的提取更加困难,而时钟信号的不准确性会降低整个系统的性能。本文我们给出一种改进的时钟恢复算法原理,算法主要包含简单有效的插值滤波模块,改进的Gardener算法和快速收敛的PLL。该算法可以适用于宽带无线通信系统中的数字接收机中,采用该算法的数字接收系统已经用FPGA验证通过。