An integrated multi-objective immune algorithm for optimizing the wire bonding process of integrated circuits

Optimization of the wire bonding process of an integrated circuit (IC) is a multi-objective optimization problem (MOOP). In this research, an integrated multi-objective immune algorithm (MOIA) that combines an artificial immune algorithm (IA) with an artificial neural network (ANN) and a generalized Pareto-based scale-independent fitness function (GPSIFF) is developed to find the optimal process parameters for the first bond of an IC wire bonding. The back-propagation ANN is used to establish the nonlinear multivariate relationships between the wire boning parameters and the multi-responses, and is applied to generate the multiple response values for each antibody generated by the IA. The GPSIFF is then used to evaluate the affinity for each antibody and to find the non-dominated solutions. The “Error Ratio” is then applied to measure the convergence of the integrated approach. The “Spread Metric” is used to measure the diversity of the proposed approach. Implementation results show that the integrated MOIA approach does generate the Pareto-optimal solutions for the decision maker, and the Pareto-optimal solutions have good convergence and diversity performance.     

基于FPGA的SM3算法优化设计与实现

介绍SM3密码杂凑算法的基本流程,基于现场可编程门阵列(FPGA)平台,设计SM3算法IP核的整体架构,对关键逻辑进行优化设计。选用Cyclone系列器件作为目标器件,与现有算法进行实现比较,结果表明SM3算法IP核耗费较少的逻辑单元和存储单元,具有最高的算法效率,可为密码片上系统产品的开发提供算法引擎支持。     

DMC在线优化的分布式求解在FPGA上的实现

针对高维系统的动态矩阵控制（DMC）,为克服单-FPGA计算资源有限的困难,提出以分布方式求解DMC的在线优化问题。采用多个FPGA,并通过板间的高速串行通道RocketlO交换信息,建立分布式求解系统。实验结果表明,分布式求解系统能有效解决DMC在线优化问题。     

基于OTDM的FBG传感器网络超高速解调系统的设计

基于光纤Bragg光栅(FBG)和光时分复用(OTDM)的基本原理研究匹配光栅应变传感器网络的高速解调问题。给出了运用FPGA+ARM的匹配光栅应变解调系统设计,实现了多个FBG信道的同时监测。重点在通过寻峰算法寻到峰值的情况下,结合一种复合滤波算法(限幅法+滑动滤波法),极大地抑制了光路和电路中产生的噪声,将峰值功率变化范围由-1.03 dB压缩到-0.31 dB,使得所设计的系统能够在多种环境中应用,具有重要的参考价值。     

A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA

Evolvable hardware is a system that modifies its architecture and behavior to adapt with changes of the environment. It is formed by reconfigurable processing elements driven by an evolutionary algorithm. In this paper, we study a reconfigurable HexCell-based systolic array architecture for evolvable systems on FPGA. HexCell is a processing element with a tile-able hexagonal-shaped cell for reconfigurable systolic arrays on FPGAs. The cell has three input ports feed into an internal functional-unit connected to three output ports. The functional-unit is configured using dynamic partial reconfiguration (DPR), and the output ports, in contrast, are configured using virtual reconfiguration circuit (VRC). Our proposed architecture combines the merits of both DPR and VRC to achieve fast reconfiguration and accelerated evolution. A HexCell-based 4 × 4 array was implemented on FPGA and utilized 32.5% look-up tables, 31.3% registers, and 1.4% block RAMs of Artix-7 (XC7Z020) while same-size conventional array consumed 8.7%, 5.1%, and 20.7% of the same FPGA, respectively. As a case study, we used an adaptive image filter as a test application. Results showed that the fitness of the best filters generated by our proposed architecture were generally fitter than those generated by the conventional state-of-the-art systolic array on the selected application. Also, performing 900,000 evaluations on HexCell array was 2.6 × faster than the conventional one.     

基于蚁群优化算法的虚拟现场可编程门阵列部署策略

针对可重构密码资源池中,如何在最少的现场可编程门阵列（FPGA）上部署虚拟FPGA （vFPGA）的问题,结合FPGA的工作特点和应用场景的需求,在传统蚁群算法的基础上进行了优化,提出了一个基于蚁群优化（ACO）算法的vFPGA部署策略。首先,通过赋予蚂蚁资源状态感知的能力实现各个FPGA之间的负载均衡,同时避免频繁的vFPGA迁移;其次,设计预留空间,有效减少因为租户需求动态变化带来的服务等级协议（SLA）冲突;最后,对CloudSim进行功能扩展,使用合成的工作流进行仿真实验,对该策略性能进行评估。实验结果表明,所提策略可以在保证系统服务质量的前提下,提高FPGA资源利用率,减少FPGA使用量。     

一类复杂芯片的FPGA验证

介绍了模块层次构造算法和改进的K-L算法对设计进行划分，有效地减少了FPGA间的互连信号数。通过引脚复用（CPM）的方法，解决了多块FPGA间互连过多而引起的引脚不足问题。另一方面，FPGA的运行频率远远低于实际芯片的工作频率，通过在接口设置延迟寄存器和修改系统软件可以准确评估实际流片芯片的性能，实验的误差在2%以内。     

基于U-Net结构的生成式多重对抗隐写算法

人工智能的发展为信息隐藏技术带来越来越多的挑战,提高现有隐写方法的安全性迫在眉睫.为提高图像的信息隐藏能力,提出一种基于U-Net结构的生成式多重对抗隐写算法.所提算法通过生成对抗网络与隐写分析器优化网络、隐写分析对抗网络间的多重对抗训练,构建生成式多重对抗隐写网络模型,生成适合信息隐写的载体图像,提高隐写图像抗隐写分析能力;同时,针对现有生成对抗网络只能生成随机图像,且图像质量不高的问题,设计基于U-Net结构的生成式网络模型,将参考图像的细节信息传递到生成载体图像中,可控地生成高质量目标载体图像,增强信息隐藏能力;其次,采用图像判别损失、均方误差(MSE)损失和隐写分析损失动态加权组合作为网络迭代优化总损失,保障生成式多重对抗隐写网络快速稳定收敛.实验表明,基于U-Net结构的生成式多重对抗隐写算法生成的载体图像PSNR最高可达到48.60 dB,隐写分析器对生成载体图像及其隐写图像的判别率为50.02%,所提算法能够生成适合信息嵌入的高质量载体图像,保障隐写网络快速稳定收敛,提高了图像隐写安全性,可以有效抵御当前优秀的隐写分析算法的检测.     

一种FPGA抗辐射布线算法设计

随着集成密度的增大以及工作电压的降低,基于SRAM的FPGA芯片更加容易受到单粒子翻转的影响。提出了一种基于通用布局布线工具VPR的抗辐射布线算法,通过改变相关布线资源节点的成本函数,来减少因单粒子翻转引起的桥接错误,并与VPR比较下板测试结果。实验结果表明,该布线算法可以使芯片的容错性能提升20%左右,并且不需要增加额外的硬件资源或引入电路冗余。     

基于RGB-D图像核描述子的物体识别方法

针对传统的颜色-深度（RGB-D）图像物体识别的方法所存在的图像特征学习不全面、特征编码鲁棒性不够等问题,提出了基于核描述子局部约束线性编码（KD-LLC）的RGB-D图像物体识别方法。首先,在图像块间匹配核函数基础上,应用核主成分分析法提取RGB-D图像的3D形状、尺寸、边缘、颜色等多个互补性核描述子;然后,分别对它们进行LLC编码及空间池化处理以形成相应的图像编码向量;最后,把这些图像编码向量融合成具有鲁棒性、区分性的图像表示。基于RGB-D数据集的仿真实验结果表明,作为一种基于人工设计特征的RGB-D图像物体识别方法,由于所提算法综合利用深度图像和RGB图像的多方面特征,而且对传统深度核描述子的采样点选取和紧凑基向量的计算这两方面进行了改进,使得物体类别识别率达到86.8%,实体识别率达到92.7%,比其他同类方法具有更高的识别准确率。     

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Radiation-induced single bit upsets (SBUs) and multi-bit upsets (MBUs) are more prominent in Field Programmable Gate Arrays (FPGAs) due to the presence of a large number of latches in the configuration memory (CM) of FPGAs. At the same time, SBUs and MBUs in the CM can permanently or temporarily affect the hardware circuit implemented on FPGA. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from permanent faults arising due to such SBUs and MBUs. Different existing techniques used to mitigate the effect of soft errors in FPGA have high overhead and their implementations are also quite complex. In this paper, we have proposed efficient single bit as well as multi-bit error correcting methods to correct errors in the CM of FPGAs using simple parity equations and Erasure code. These codes are easy to implement, and the needed decoding circuits are also simple. Use of Dynamic Partial Reconfiguration (DPR) along with a simple hardware scheduling algorithm based download manager helps to perform the error correction in the CM without suspending the operations of the other hardware blocks. We propose a first of its kind methodology for novel transient fault correction using efficient error correcting codes with hardware scheduling for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like fault recovery time, power consumption, resource overhead and error correction efficiency to estimate the performance of our proposed methods.     

基于聚类预处理和支持向量机的模拟电路故障诊断技术

支持向量机（SVM）最初源于两种分类问题，用于存在较多故障模式的模拟电路诊断问题，易造成识别重叠区域。为此提出了利用动态聚类算法作为SVM预分类器的故障诊断方法，首先采用模糊C-均值（FCM）算法对训练样本进行聚类，然后分别对两大类进行内部的子聚类，每一次的聚类都产生两种模式并对各个模式内的故障模式样本训练产生对应的SVM网络，最后采用二叉树形式把所有的模式分开。实验结果表明，采用该方法对测试样本的诊断正确率可以达到99%以上。     

Applying Genetic Parallel Programming to Synthesize Combinational Logic Circuits

Experimental results show that parallel programs can be evolved more easily than sequential programs in genetic parallel programming (GPP). GPP is a novel genetic programming paradigm which evolves parallel program solutions. With the rapid development of lookup-table-based (LUT-based) field programmable gate arrays (FPGAs), traditional circuit design and optimization techniques cannot fully exploit the LUTs in LUT-based FPGAs. Based on the GPP paradigm, we have developed a combinational logic circuit learning system, called GPP logic circuit synthesizer (GPPLCS), in which a multilogic-unit processor is used to evaluate LUT circuits. To show the effectiveness of the GPPLCS, we have performed a series of experiments to evolve combinational logic circuits with two- and four-input LUTs. In this paper, we present eleven multi-output Boolean problems and their evolved circuits. The results show that the GPPLCS can evolve more compact four-input LUT circuits than the well-known LUT-based FPGA synthesis algorithms.     

XDL网表的前向电路图生成算法

作为描述FPGA（Field Programmable Gate Array）电路网表的XDL（Xilinx Design Language）描述文件，不仅能用于解析抽取FPGA设计的Inst电路单元和Net电路信号，而且能用于构建FPGA电路网表中信号传播的前向电路图模型。采用有向超图来构建FPGA电路网表中信号的前向拓扑关系，其中FPGA电路单元的有效管脚表示为超图结点，管脚间的外部连线、管脚内的电路逻辑功能表示为有向超边。给出了XDL网表级电路描述文件编译所需的EBNF表达式，提出了基于有向超图的XDL网表的前向电路图生成算法，进行了算法的时空复杂度分析。在Windows平台下基于RapidSmith开源软件实现了前向电路图生成算法，并选用基于Virtex-4型号FPGA测试用例的XDL网表，生成相应的前向电路图以验证XDL网表的前向电路图生成算法的正确性和有效性。     

The hybrid field-programmable architecture

The authors propose a new architecture that combines two existing technologies: lookup-table-based FPGAs and complex programmable logic devices based on PLA-like blocks. Their mapping results indicate that on average LUT-based FPGAs require 78% more area than their hybrid FPGA, while providing roughly the same circuit depth     

用动态规划法求解延时/面积最小化工艺映射

本文提出了一个求解延时／面积最小化工艺映射动态规划法．它首先基干线性延时模型，给出了用动态规划法求解延时最小化工艺映射的步骤；然后从树型网络的面积计算公式入手，用动态规划法近似计算面积最小化工艺映射；最后用“线性加权和法”把延时／面积最小化工艺映射转变为单目标最优化问题求解．     

An improved constrained differential evolution algorithm for unmanned aerial vehicle global route planning

This paper formulates the global route planning problem for the unmanned aerial vehicles (UAVs) as a constrained optimization problem in the three-dimensional environment and proposes an improved constrained differential evolution (DE) algorithm to generate an optimal feasible route. The flight route is designed to have a short length and a low flight altitude. The multiple constraints based on the realistic scenarios are taken into account, including maximum turning angle, maximum climbing/gliding slope, terrain, forbidden flying areas, map and threat area constraints. The proposed DE-based route planning algorithm combines the standard DE with the level comparison method and an improved strategy is proposed to control the satisfactory level. To show the high performance of the proposed method, we compare the proposed algorithm with six existing constrained optimization algorithms and five penalty function based methods. Numerical experiments in two test cases are carried out. Our proposed algorithm demonstrates a good performance in terms of the solution quality, robustness, and the constraint-handling ability.     

ZigBee网络节点基带处理器的设计与实现

设计一款新型符合ZigBee协议的无线传感器网络节点基带处理器。提出一种O-QPSK非相干解调的同步相关解码方式,解决了解调电路的结构冗余问题,降低了数字接收机的信噪比。设计收发控制器完成发送与接收流程的管理,通过模式切换和软件平台的优化降低了整个节点芯片的工作功耗和面积。通过Altera Stratix S80 FPGA平台进行测试验证,结果符合设计要求。     

Parallel chaos optimization algorithm with migration and merging operation

Chaos optimization algorithm (COA) utilizes the chaotic maps to generate the pseudo-random sequences mapped as the decision variables for global optimization applications. A kind of parallel chaos optimization algorithm (PCOA) has been proposed in our former studies to improve COA. The salient feature of PCOA lies in its pseudo-parallel mechanism. However, all individuals in the PCOA search independently without utilizing the fitness and diversity information of the population. In view of the limitation of PCOA, a novel PCOA with migration and merging operation (denoted as MMO-PCOA) is proposed in this paper. Specifically, parallel individuals are randomly selected to be conducted migration and merging operation with the so far parallel solutions. Both migration and merging operation exchange information within population and produce new candidate individuals, which are different from those generated by stochastic chaotic sequences. Consequently, a good balance between exploration and exploitation can be achieved in the MMO-PCOA. The impacts of different one-dimensional maps and parallel numbers on the MMO-PCOA are also discussed. Benchmark functions and parameter identification problems are used to test the performance of the MMO-PCOA. Simulation results, compared with other optimization algorithms, show the superiority of the proposed MMO-PCOA algorithm.