红外焦平面硅基通孔加工及电极互连技术

通过硅通孔技术实现红外焦平面电极垂直互连,提高像元占空比,缩短了互连引线长度,降低了信号延迟。用单晶硅湿法刻蚀方法形成通孔,利用直写技术将耐高温Ag-Pd导体浆料填充通孔,实现红外焦平面阵列底电极与硅基片背面倒装焊凸点互连。     

MEMS单晶硅加热雾化芯片设计与制作

为实现高粘度液体的雾化,提出一种微机电系统(MEMS)单晶硅快速加热雾化芯片。对单晶硅加热芯片结构进行了设计,芯片为10 mm×10 mm的方形,布置了168个边长为500μm的方形雾化孔。通过ANSYS有限元软件进行了电—热耦合仿真,以评估其温度分布均匀性。衬底采用5×10~(-3)Ω·cm的4 in(l in=2.54 cm)N型(100)硅片,基于各向异性湿法腐蚀工艺完成了微孔阵列和芯片的制造。测试结果表明:室温下芯片电阻约为0.6Ω,且电阻值与温度呈正相关;芯片温度分布均匀,最低温与最高温相差约12.7%;施加3.7 V电压时,芯片在4 s内可升温至300℃,能够实现对甘油的快速雾化。该芯片结构和制作工艺简单,易于实现批量制造。     

一种适用无源RFID的集成加速度传感器设计

针对射频识别（ RFID）与无线传感器网络（ WSNs）融合研究的需要,基于0.35μm CMOS工艺设计了一种集成加速度传感器。传感器单元采用从单晶硅衬底的背面进行深反应离子刻蚀工艺,背面刻蚀完成后再正面对金属和介质复合层进行各向异性刻蚀。集成电容式传感器接口电路基于锁相环原理,将传感器信号转移到频率域处理,避免了高功耗的A/D转换器的使用,直接完成电容/数字转换。后期测试结果显示：所设计的集成加速度传感器线性度好,稳定性高,功耗低,适合无源RFID及其它超低功耗应用设计。     

TMAH腐蚀液制作硅微结构的研究

通过各向异性腐蚀硅微结构工艺,研究了四甲基氢氧化铵(TMAH)腐蚀液的特性,包括硅(100)晶面腐蚀速率与TAMH溶液浓度、温度、pH值以及过硫酸铵添加剂的关系,并采用原子力显微镜研究了不同腐蚀条件下硅的表面形貌,研究表明:随TMAH溶液的浓度的降低和腐蚀温度的提高,腐蚀速率提高,硅腔的表面粗糙度增大;过硫酸铵添加剂明显改善了硅微腔的表面平整度.本研究所确定的最佳腐蚀工艺条件为:溶液中TMAH浓度为25%,过硫酸铵添加剂浓度为3%,腐蚀温度80℃.在此工艺条件下腐蚀出了深度为230 μm、表面粗糙度小于50 nm的硅微腔.     

一种新颖的基于离子束刻蚀的纳米沟道制备技术

研究了一种新颖的基于MEMS工艺中离子束刻蚀的纳米沟道制备技术,通过研究离子束刻蚀微米级线条时,离子束刻蚀角度与刻蚀的轮廓形状之间的关系,在2μm线条内刻蚀出纳米沟道所需要的掩模图形,并结合KOH的各向异性腐蚀,成功获得了纳米沟道阵列.在两种不同的离子束刻蚀条件下,在2 μm图形内分别制备出单纳米沟道和双纳米沟道,最小宽度可达440 nm.     

基于C-SOI工艺的一维MEMS电容式超声传感器阵列

提出了一种新的基于C-SOI工艺制备的电容式微加工超声传感器(CMUT)的方法.通过对加工过程中一些关键工艺步骤进行测试,发现所加工的微传感器尺寸与设计尺寸基本一致,且刻蚀的空腔高度均匀,键合效果良好,证明了工艺流程的可行性.此外,通过对所加工的传感器阵列进行测试发现,各阵元谐振频率和静态电容具有良好的一致性,说明以C-SOI工艺加工的CMUT器件满足设计要求,且适宜加工大阵列,这种加工技术使得加工成像阵列成为可能.     

集成化触觉阵列传感器的研制

介绍了一种集成化单晶硅触觉阵列传感器。该传感器共有 10 0个触觉单元 ,芯片尺寸为 2 5mm×2 5mm ,厚度小于 10mm。在制造工艺上 ,把CMOS工艺和半导体平面工艺融为一体 ,利用MEMS技术在每个触觉单元上制造了触觉受力点 ,易于感受所触物体 ,其测试、记录过程由计算机完成。该种传感器具有一定的开发价值和应用前景。     

二氧化硅的干法刻蚀工艺研究

主要研究了二氧化硅的干法刻蚀工艺.运用反应离子刻蚀设备(RIE150×4)进行了一系列的刻蚀实验,采用不同的工艺条件对二氧化硅进行选择刻蚀工艺研究,得出了不同工艺条件对应的刻蚀速率、均匀性、选择比等刻蚀参数,并对结果进行了比较与分析,得到了相对最佳的工艺条件.     

等离子体和反应离子刻蚀硅的各向异性 及均匀性实验研究

在反应离子刻蚀(RIE)及等离子体刻蚀(PE)设备中,分别采用CF_4,SF_6,NF_3和C_7F_(14),腐蚀剂气体,对(100)Si进行刻蚀.研究了工艺条件对刻蚀各向异性及均匀性的影响.结果表明,RIE的各向异性与均匀性均优于PE.RIE的各向异性值A与刻蚀气体中的添加剂成份有关,添加20%Ar时A最大值为5.4;添加20%C_2F_5Cl时,A值可高达10以上.在RIE中,CF_4和NF_3,的刻蚀均匀性优于SF_6,最佳刻蚀均匀性平均值优于5%,添加剂对刻蚀均匀性没有明显的影响.而PE显示各向同性的刻蚀特征,均匀性约为16.5%.并对各向异性及均匀性的起因作了解释.     

AlN陶瓷微热板MEMS传感器阵列设计与工艺实现

针对陶瓷基微热板MEMS器件难以微加工,器件表面加热Pt膜使用普通正性光刻胶难以实现光刻剥离的工艺难点问题,提出了激光微加工和柔性机械剥离相结合的微加工方法。以AlN陶瓷为衬底基片,采用激光微加工技术实现热隔离刻蚀体加工,刻蚀梁宽可达0.2 mm。采用柔性机械剥离工艺制备方法解决普通正性光刻胶形成倒梯形凹槽Pt膜难实现图形化问题,可在复杂表面特性的陶瓷基衬底上实现Pt膜剥离线宽10μm。同时利用有限元法进行传感器阵列设计和热结构仿真,验证设计工艺的可行性。     

基于FDM工艺结构的3D打印机高温喷头结构优化研究

打印机喷头结构不合理,会出现温度场分布不均现象,导致喷头堵塞,影响打印速度。为此,本文提出基于FDM工艺结构的3D打印机高温喷头结构优化研究。设计三维CAD模型,控制喷头移动,结合喷头结构,计算热传导遵循的傅里叶定律与稳定热传导规律;从模型“台阶效应”、挤出丝材两方面探究影响喷头打印效果的主要因素,在确保打印质量前提下,利用磁制冷方法,经过多次调试,确定最佳压力值,优化送丝机构,设计制冷装置,实现高温喷头结构优化。仿真实验证明,优化后的高温喷头温度分布更为合理,有效避免喷头堵塞现象,可实现高速度持续打印。     

High-resolution long-array thermal ink jet printhead fabricated by anisotropic wet etching and deep Si RIE

This paper describes the fabrication and characterization of a thermal ink jet (TIJ) printhead suitable for high speed and high-quality printing. The printhead has been fabricated by dicing the bonded wafer, which consists of a bubble generating heater plate and a Si channel plate. The Si channel plate consists of an ink chamber and an ink inlet formed by KOH etching, and a nozzle formed by inductively couple plasma reactive ion etching (ICP RIE). The nozzle formed by RIE has squeezed structures, which contribute to high-energy efficiency of drop ejector and, therefore, successful ejection of small ink drop. The nozzle also has a dome-like structure called channel pit, which contributes to high jetting frequency and high-energy efficiency. These two wafers are directly bonded using electrostatic bonding of full-cured polyimide to Si. The adhesive-less bonding provided an ideal shaped small nozzle orifice. Use of the same material (Si substrate) in heater plate and channel plate enables the fabrication of high precision long printhead because no displacement and delamination occur, which are caused by the difference in thermal expansion coefficient between the plates. With these technologies, we have fabricated a 1" long printhead with 832 nozzles having 800 dots per inch (dpi) resolution and a 4 pl. ink drop volume.     

A thermal inkjet printhead with a monolithically fabricated nozzleplate and self-aligned ink feed hole

A monolithic thermal inkjet printhead has been developed and demonstrated to operate successfully by combining monolithic growing of a nozzle plate on the silicon substrate and electrochemical etching of silicon for an ink feed hole. For the monolithic fabrication, a multiexposure and single development (MESD) technique and Ni electroplating are used to form cavities, orifices, and the nozzle plate. Electrochemical etching, as a back-end process, is applied to form an ink feed hole through the substrate, which is accurately aligned with the frontside pattern without any backside mask. The etch rate is nearly proportional to the current density up to 50 μm/min. Experiments with a 50-μm-diameter nozzle show ink ejection up to the operating frequency of 11 kHz with an average ink dot diameter of about 110 μm for 0.3-A, 5-μs current pulses     

Hole-type two-dimensional photonic crystal fabricated in silicon on insulator wafers

We report the realization of two-dimensional (2D) photonic crystal (PhC) holes array using synthesized processing techniques of deep UV lithography, time-multiplexed reactive ion etching (TMRIE) and focus ion beam (FIB) etching. In this study, mixed density of holes and waveguide patterns of 2D PhC structures was first formed in silicon on insulator wafers through use of a scanner. Ultra wide grooves were then defined, aligned to the deep submicron size devices. Following deep etching of more than 50 μm by TMRIE, PhC structures were then revealed for device etching. Such design of fabrication process allows realization of disparate pattern dimensions and also etching depths. Through avoidance of etch lag effect, notching of devices at interface of device silicon and buried oxide layer was avoided. At the same time, through a singular FIB etch in the final step of the process following buried oxide release for PhC structures on critical dimension structures, severe loading effects of such structures were avoided to enable a wide process window of lithography and etch.     

An advanced reactive ion etching process for very high aspect-ratio sub-micron wide trenches in silicon

This paper reports on a practical modification of the two-step time-multiplexed plasma etching recipe (also known as the Bosch process) to achieve high aspect-ratio sub-micron wide trenches in silicon. Mixed argon and oxygen plasma depassivation steps are introduced in between the passivation and etching phases to promote the anisotropic removal of the passivation layer at the base of the trench. Argon does not chemically react with polymers and silicon and removes the passivation layer only by physical sputtering. Therefore, it results in a highly anisotropic polymer etching process. This recipe can be easily integrated on conventional ICP equipment and the scalloping on the trench sidewall can potentially be reduced in size to less than 50 nm. To clean up all the passivation residues, a short oxygen plasma step is also added at the end of the cycle that effectively improves the uniformity of the etching profile over various opening sizes. Excellent anisotropy of the inserted argon depassivation step facilitates narrow trenches down to 130 nm wide and gap aspect-ratios as high as 40:1, extending the application of deep reactive ion etching (DRIE) processes into a new broad regime.     

Tungsten-Based SOI Microhotplates for Smart Gas Sensors

This paper is concerned with the design, fabrication, and characterization of novel high-temperature silicon on insulator (SOI) microhotplates employing tungsten resistive heaters. Tungsten has a high operating temperature and good mechanical strength and is used as an interconnect in high temperature SOI-CMOS processes. These devices have been fabricated using a commercial SOI-CMOS process followed by a deep reactive ion etching (DRIE) back-etch step, offering low cost and circuit integration. In this paper, we report on the design of microhotplates with different diameters (560 and 300 $muhbox{m}$) together with 3-D electrothermal simulation in ANSYS, electrothermal characterization, and analytical analysis. Results show that these devices can operate at high temperatures (600 $^{circ}hbox{C}$ ) well beyond the typical junction temperatures of high temperature SOI ICs (225 $^{circ}hbox{C}$), have ultralow dc power consumption (12 mW at 600 $^{circ}hbox{C}$), fast transient time (as low as 2-ms rise time to 600 $^{circ}hbox{C}$), good thermal stability, and, more importantly, a high reproducibility both within a wafer and from wafer to wafer. We also report initial tests on the long-term stability of the tungsten heaters. We believe that this type of SOI microhotplate could be exploited commercially in fully integrated microcalorimetric or resistive gas sensors. $hfill$[2007-0275]      

Parameter optimization for an ICP deep silicon etching system

The paper aims at investigating the parameter optimization of silicon micro- and nano-sized etching by an inductive coupled plasma-reactive ion etching system. The source power and the SF₆ gas pressure are two main parameters that dominate etching. A pre-test is conducted to estimate the process window of the SF₆ gas pressure at some given source powers. The process window is a parameter range in which the etching result is acceptable but may not be the best. In order to achieve excellent etching quality, the Taguchi experimental method is applied to evaluate parameters and find their optimum conditions. With the source power and SF₆ gas pressure being set into the process window, four parameters, which are the substrate temperature, the bias power, the gas cycle time and the C₄F₈ gas flow rate, are evaluated and optimized for micro- and nano-sized etching. An impressive result, 200-nm-diameter pillar array with the pitch of 400 nm, is realized.     

The MEMSNAS process: microloading effect for micromachining 3-D structures of nearly all shapes

We propose a technological process for microfabrication of three-dimensional (3-D) structures with nearly all shapes. This is a one-mask process that uses equipment, widespread in the microelectronics laboratories and industry. The main idea is to take advantage from the microloading effect of reactive ion etching (RIE) in order to obtain multiple levels of heights in an array of microholes of different diameters. A 3-D profile results from an overlap of the neighboring microholes due to the isotropic nature of the etching. The final continuous and smooth 3-D structure is obtained after removal of the mask material and a second isotropic RIE step. This fabrication process was validated with the realization of various 3-D structures including microlenses, etched in a 30 /spl mu/m deep cavity, with 375 /spl mu/m in radius and 10 /spl mu/m in height (sag). The resulting structures have shown a roughness down to 25 nm. A quantitative experimental study led to the calibration of three different processes and to an empirical theoretical model, which can serve as a basis of design rules for further fabrication of 3-D microstructures.     

Rapid soda-lime glass etching process for producing microfluidic channels with higher aspect ratio

This paper presents a simple method to produce microfluidic channels in soda-lime glasses with the aspect ratio >0.5 utilizing a modified wet etching protocol. A low-cost positive photoresist (PR) layer is used as the etching mask for the wet etching process. Prior to the PR and primer coating procedure, a UV activation process is adopted for enhancing the binding strength of the hexamethyldisilazane primer layer and the glass substrate, resulting in an better adhesion for the PR layer. A fast etching recipe is also developed by increasing the acidity and the temperature of the buffered oxide (BOE) etchant. Since the photoresist etching mask does not peel during the etching process shortly, the structure of the etching mask forms a barrier and results in a different diffusion rate for the etchant inside the etched trench structure. A slower etching rate for the glass is observed at the undercut region such that the proposed anisotropic etching pattern can be achieved. Results show that the etching rate of the modified glass etching process is as high as 7.7 μm/min which is much faster than that of pure BOE etchant (0.96 μm/min). Sealed microfluidic channel with the aspect ratio of around 0.62 is produced with the developed method. The method developed in the present study provides a rapid and efficient way to produce microfluidic channels with higher aspect ratio.     

A PZT-driven atomizer based on a vibrating flexible membrane and a micro-machined trumpet-shaped nozzle array

This paper presents the design, and fabrication of a PZT-driven atomizer based on a flexible membrane and a micro-machined trumpet-shaped nozzle array. Tests were conducted to demonstrate that the developed atomizer can produce fine droplets. The atomizer uses a PZT bimorph plate attached to a liquid-proof HDPE membrane with a low Young’s modulus to generate a pressure wave in the liquid reservoir. The trumpet-shaped micro-nozzle array is fabricated using a surface micromachining technique and an electroplating process. The fabrication process allows the use of a low resolution photomask to fabricate a high feature-sized trumpet-nozzle array. The SMD values of the ejected droplets and the flow rate of the fabricated atomizer are measured experimentally as a function of the operating frequency and the nozzle diameter for liquids of various viscosities. The relationship between the droplet size distribution and the SMD value is also explored. The experimental results show that the atomizer is capable of generating droplets with an SMD of 4.6 μ at a flow rate of 2.5 g/min. Hence, the atomizer has the potential for use in many applications.