Area and delay efficient GDI based accuracy configurable adder design

Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.     

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata

Application of quantum-dot is a promising technology for implementing digital systems at nano-scale. QCA supports the new devices with nanotechnology architecture. This technique works based on electron interactions inside quantum-dots leading to emergence of quantum features and decreasing the problem of future integrated circuits in terms of size. In this paper, we will successfully design, implement and simulate a new full adder based on QCA with the minimum delay, area and complexities. Also, new XOR gates will be presented which are used in 8-bit controllable inverter in QCA. Furthermore, a new 8-bit full adder is designed based on the majority gate in the QCA, with the minimum number of cells and area which combines both designs to implement an 8-bit adder/subtractor in the QCA. This 8-bit adder/subtractor circuit has the minimum delay and complexity. Being potentially pipeline, the QCA technology calculates the maximum operating speed.     

VLIW数字信号处理器64位可重构加法器的设计

描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。该加法器高度可重构，可以支持2个64位数据的加法运算、4个32位数据的加法运算、8个16位数据的加法运算以及16个8位数据的加法运算。它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点，使得加法器的面积和连线减少了50%，而延时与加法器的长度的对数成正比。仿真结果表明，在典型工作条件下，采用0.18μm工艺库标准单元，其关键路径的延时为0.83ns，面积为0.149mm2，功耗仅为0.315mW。     

Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology

This paper focuses on a novel design of an adder/subtractor-based incrementer/decrementer using quantum-dot cellular automata (QCA) technology. QCA is a promising nanotechnology that offers new techniques of computation and data transmission. We use the multilayer crossover technique in the proposed designs to achieve low latency and area for the scalability feature. Moreover, new designs of QCA half and full adders are proposed to improve the operating speed of the incrementer/decrementer. The working of the proposed designs is analyzed via the QCA simulator tool, and the results are compared with previous studies in terms of cell count, area, and latency. According to the analysis, the presented designs perform well; for example, the proposed 4-bit incrementer design shows an improvement of 65 % in terms of area usage and 3.2 times lower latency compared to its existing counterpart.     

VLSI中加法器的一种高效自测试设计

基于算术加法测试生成,提出了VLSI中加法器的一种自测试方案:加法器产生自身所需的所有测试矢量.通过优化测试矢量的初值改进这些测试矢量,提高了其故障侦查、定位能力.借助于测试矢量左移、逻辑与操作等方式对加法器自测试进行了设计.对8位、16位、32位行波、超前进位加法器的实验结果表明,该自测试能实现单、双固定型故障的完全测试,其单、双故障定位率分别达到了95.570%,72.656%以上.该自测试方案可实施真速测试且不会降低电路的原有性能,其测试时间与加法器长度无关.     

A low energy dual-mode adder

VLSI designs are typically data-independent and as such, they must produce the correct result even for the worst-case inputs. Adders in particular assume that addition must be completed within prescribed number of clock cycles, independently of the operands. While the longest carry propagation of an n-bit adder is n bits, its expected length is only O(log₂ n) bits. We present a novel dual-mode adder architecture that reduces the average energy consumption in up to 50%. In normal mode the adder targets the O(log₂ n)-bit average worst-case carry propagation chains, while in extended mode it accommodates the less frequent O(n)-bit chain. We prove that minimum energy is achieved when the adder is designed for O(log₂ n) carry propagation, and present a circuit implementation. Dual-mode adders enable voltage scaling of the entire system, potentially supporting further overall energy reduction. The energy-time tradeoff obtained when incorporating such adders in ordinary microprocessor’s pipeline and other architectures is discussed.     

Effective RCA design using quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is a transistor less technology alternative to CMOS for developing low-power, high speed digital circuits. Adder circuits are broadly employed in all digital computation systems. In this paper, a novel coplanar QCA full adder circuit is proposed which is designed with minimum number of QCA cells. The proposed full adder requires only 13 QCA cells, an area of 0.008 μm² and delay of about 2 clock cycles to implement its function. Then an efficient 4-bit Ripple Carry Adder (RCA) is designed based on the proposed full adder that performs higher end addition in an effective way. Simulations results are obtained precisely using QCA designer tool version 2.0.3. Also the simulation results shows that the proposed 4-bit Ripple Carry Adder (RCA) requires only 70 QCA cells, an area of 0.18 μm² and delay of about 5 clock cycles to implement its function with enhanced performance in terms of latency, area and QCA Cost. From the comparisons, it is found that our work achieves over 55% improvement in QCA cell count.     

A fast inner product processor based on equal alignments

Inner product computation is an important operation, invoked repeatedly in matrix multiplications. A high-speed inner product processor can be very useful (among many possible applications) in real-time signal processing. This paper presents the design of a fast inner product processor, with appreciably reduced latency and cost. The inner product processor is implemented with a tree of carry-propagate or carry-save adders; this structure is obtained with the incorporation of three innovations in the conventional multiply/add tree: (1) The leaf-multipliers are expanded into adder subtrees, thus achieving an O(log Nb) latency, where N denotes the number of elements in a vector and b the number of bits in each element. (2) The partial products, to be summed in producing an inner product, are reordered according to their “minimum alignments.” This reordering brings approximately a 20% saving in hardware—including adders and data paths. The reduction in adder widths also yields savings in carry propagation time for carry-propagate adders. (3) For trees implemented with carry-save adders, the partial product reordering also serves to truncate the carry propagation chain in the final propagation stage by 2 log b − 1 positions, thus significantly reducing the latency further. A form of the Baugh and Wooley algorithm is adopted to implement two's complement notation with changes only in peripheral hardware.     

Micropneumatic Digital Logic Structures for Integrated Microdevice Computation and Control

It is shown that microfabricated polydimethylsiloxane membrane valve structures can be configured to function as transistors in pneumatic digital logic circuits. Using the analogy with metal-oxide-semiconductor field-effect transistor circuits, networks of pneumatically actuated microvalves are designed to produce pneumatic digital logic gates (AND, OR, NOT, NAND, and XOR). These logic gates are combined to form 4- and 8-bit ripple-carry adders as a demonstration of their universal pneumatic computing capabilities. Signal propagation through these pneumatic circuits is characterized, and an amplifier circuit is demonstrated for improved signal transduction. Propagation of pneumatic carry information through the 8-bit adder is complete within 1.1 s, demonstrating the feasibility of integrated temporal control of pneumatic actuation systems. Integrated pneumatic logical systems reduce the number of off-chip controllers required for lab-on-a-chip and microelectromechanical system devices, allowing greater complexity and portability. This technology also enables the development of digital pneumatic computing and logic systems that are immune to electromagnetic interference.     

Decimal addition on FPGA based on a mixed BCD/excess-6 representation

Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition.     

Delay and area efficient approximate multiplier using reverse carry propagate full adder

The performance and power of error resilient applications will rise with a decrease in designing complexness due to approximate computing. This paper includes the new method for the approximation of multipliers. Variable likelihood terms are produced by the alteration of partial products of the multiplier. Based on the probability statistics, the accumulation of altered partial products leads to the variation of logic complexity. Here the estimate is implemented in 2 variables of 16-bit multiplier and in the final stage with reverse carry propagate adder(RCPA). The reverse carry propagate adder have carry signal propagation from the most significant bit(MSB) to the least significant bit(LSB), which results in greater relevance to the input carry than the output carry. The technique of carry circulation in reverse order with delay variations increases the stability. Utilizing the RCPA in approximate multiplier provide 21% and 7% improvements in area and delay. On comparing, this structure is resilient to delay variations than the ideal approximate adder.     

Area and power efficient pipelined hybrid merged adders for customized deep learning framework for FPGA implementation

With the rapid growth of deep learning and neural network algorithms, various fields such as communication, Industrial automation, computer vision system and medical applications have seen the drastic improvements in recent years. However, deep learning and neural network models are increasing day by day, while model parameters are used for representing the models. Although the existing models use efficient GPU for accommodating these models, their implementation in the dedicated embedded devices needs more optimization which remains a real challenge for researchers. Thus paper, carries an investigation of deep learning frameworks, more particularly as review of adders implemented in the deep learning framework. A new pipelined hybrid merged adders (PHMAC) optimized for FPGA architecture which has more efficient in terms of area and power is presented. The proposed adders represent the integration of the principle of carry select and carry look ahead principle of adders in which LUT is re-used for the different inputs which consume less power and provide effective area utilization. The proposed adders were investigated on different FPGA architectures in which the power and area were analyzed. Comparison of the proposed adders with the other adders such as carry select adders (CSA), carry look ahead adder (CLA), Carry skip adders and Koggle Stone adders has been made and results have proved to be highly vital into a 50% reduction in the area, power and 45% when compared with above mentioned traditional adders.     

数字信号处理器中高性能可重构加法器设计

设计一款适用于高性能数字信号处理器的16位加法器。该加法器结合条件进位选择和条件“和”选择加法器的特点,支持可重构,可以进行2个16位数据或者4个8位数据的加法运算,同时对其进位链进行优化。相对于传统的条件进位选择加法器,在典型工作条件下,采用0.18μm工艺库标准单元,其延时降低46%,功耗降低5%。     

Dual-mode floating-point adder architectures

Most modern microprocessors provide multiple identical functional units to increase performance. This paper presents dual-mode floating-point adder architectures that support one higher precision addition and two parallel lower precision additions. A double precision floating-point adder implemented with the improved single-path algorithm is modified to design a dual-mode double precision floating-point adder that supports both one double precision addition and two parallel single precision additions. A similar technique is used to design a dual-mode quadruple precision floating-point adder that implements the two-path algorithm. The dual-mode quadruple precision floating-point adder supports one quadruple precision and two parallel double precision additions. To estimate area and worst-case delay, double, quadruple, dual-mode double, and dual-mode quadruple precision floating-point adders are implemented in VHDL using the improved single-path and the two-path floating-point addition algorithms. The correctness of all the designs is tested and verified through extensive simulation. Synthesis results show that dual-mode double and dual-mode quadruple precision adders designed with the improved single-path algorithm require roughly 26% more area and 10% more delay than double and quadruple precision adders designed with the same algorithm. Synthesis results obtained for adders designed with the two-path algorithm show that dual-mode double and dual-mode quadruple precision adders requires 33% and 35% more area and 13% and 18% more delay than double and quadruple precision adders, respectively.     

一种支持SIMD指令的低功耗分裂式ALU设计

在面向多媒体运算的高性能、低功耗DSP芯片MD32设计中，支持SIMD指令的分裂式、低功耗ALU设计是实现其没计目标的重要环节。该文提出了利用基于资源共享的设计思想，以超前进位加法器(Catry Look-ahead Adder)为核心构造数据处理单元，完成算术以及逻辑运算，减少了ALU模块的面积，同时均衡了不同数据通路长度，并且采用先进行数据选择，而后进行数据处理的设计原则，降低不使用模块的活动度，减少了功耗。根据Design Power分析其综合后门级实现结果，芯片面积可减少8％，功耗可减少51％。     

Performance enhancement of efficient process based on Carry-Skip Adder for IoT applications

IoT provides a platform for every device to be connected by means of a stable internet connection. The interoperability of the devices helps to communicate and exchange data between one another and increases the power consumption of devices. When creating a new IoT system or rebuilding the existing ones, the low power circuit design is considered as an essential factor. In the low power circuit design, the most challenging aspect to overcome is to reduce the leakage power, because the battery-operated devices are fast in draining energy when left long in the standby mode. Reducing the delay of a ripple carry adder can be only accomplished with Carry-Skip Adder (CSA) with minimal effort when compared to other techniques like a carry-look ahead adder. The carry skip adder belongs to the family of bypass adders, and its main aim is to improve the worst-case delay of the IoT device based on its area and power consumption. The CSA used in the proposed method for the IoT processor helps to increase the performance of the system relative to average power dissipation, leakage power, power delay product, and propagation delay.     

Towards quantum reversible ternary coded decimal adder

Quantum ternary logic is a promising emerging technology for the future quantum computing. Ternary reversible logic circuit design has potential advantages over the binary ones like its logarithmic reduction in the number of qudits. In reversible logic all computations are done in an invertible fashion. In this paper, we propose a new quantum reversible ternary half adder with quantum cost of only 7 and a new quantum ternary full adder with a quantum cost of only 14. We termed it QTFA. Then we propose 3-qutrit parallel adders. Two different structures are suggested: with and without input carry. Next, we propose quantum ternary coded decimal (TCD) detector circuits. Two different approaches are investigated: based on invalid numbers and based on valid numbers. Finally, we propose the quantum realization of TCD adder circuits. Also here, two approaches are discussed. Overall, the proposed reversible ternary full adder is the best between its counterparts comparing the figures of merits. The proposed 3-qutrit parallel adders are compared with the existing designs and the improvements are reported. On the other hand, this paper suggested the quantum reversible TCD adder designs for the first time. All the proposed designs are realized using macro-level ternary Toffoli gates which are built on the top of the ion-trap realizable ternary 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.     

Novel optimized tree-based stack-type architecture for 2n-bit comparator at nanoscale with energy dissipation analysis

Comparator is an essential building block in many digital circuits such as biometric authentication, data sorting, and exponents comparison in floating-point architectures among others. Quantum-dot Cellular Automata (QCA) is a latest nanotechnology that overcomes the drawbacks of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, novel area optimized 2n-bit comparator architecture is proposed. To achieve the objective, 1-bit stack-type and 4-bit tree-based stack-type (TB-ST) comparators are proposed using QCA. Then, two tree-based architectures of 4-bit comparators are arranged in two layers to optimize the number of quantum cells and area of an 8-bit comparator. Thus, this design can be extended to any 2n-bit comparator. Simulation results of 4-bit and 8-bit comparators using QCADesigner 2.0.3 show that there is a significant improvement in the number of quantum cells and area occupancy. The proposed TB-ST 8-bit comparator uses 2.5 clock cycles and 622 quantum cells with area occupancy of 0.49 µm² which is an improvement by 10.5% and 38%, respectively, compared to existing designs. Scaling it to a 32-bit comparator, the proposed architecture requires only 2675 quantum cells in an area of 2.05 µm² with a delay of 3.5 clock cycles, indicating 9.35% and 28.8% improvements, respectively, demonstrating the merit of the proposed architecture. Besides, energy dissipation analysis of the proposed TB-ST 8-bit comparator is simulated on QCADesigner-E tool, indicating average energy dissipation reduction of 17.3% compared to existing works.

     

Towards modular binary to gray converter design using LTEx module of quantum-dot cellular automata

A modular approach to realize the ultra-fast quantum-dot cellular automata (QCA) generic binary to gray converter is presented in this paper. The novel designs here validated fully exploit the intrinsic repetitive capabilities of the Layered T Exclusive OR (LTEx) module in the QCA domain. An efficient logic formulation of QCA design metrics like O-Cost and delay is proposed for the n-bit QCA binary to gray converter designs. The QCA implementation of n-bit LTEx binary to gray converter is compared with the conventional converters. An attempt has been made to enhance the speed of modular binary to gray converter designs. The proposed 4, 8, 16, 32, 64-bit binary to gray converters need 4.35, 15.88, 15.96, 15.7, 16.68% less O-cost and 11.57, 2.61, 9.32, 12.64, 29.25% less effective area, respectively. Thus the proposed layouts offer the smaller feature size, reduced circuit complexity exploiting the modular based design approach. The simulation results have been carried out in the renowned computer aided design tool, namely QCADesigner 2.0.3 with gallium arsenide heterostructure based parameter environment.

     

64-Bit and 128-bit DX random number generators

Extending 32-bit DX generators introduced by Deng and Xu (ACM Trans Model Comput Simul 13:299–309, 2003), we perform an extensive computer search for classes of 64-bit and 128-bit DX generators of large orders. The period lengths of these high resolution DX generators are ranging from 10¹⁹¹⁵ to 10⁵⁸²²¹. The software implementation of these generators can be developed for 64-bit or 128-bit hardware. The great empirical performances of DX generators have been confirmed by an extensive battery of tests in the TestU01 package. These high resolution DX generators can be useful to perform large scale simulations in scientific investigations for various computer systems.