Effective RCA design using quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is a transistor less technology alternative to CMOS for developing low-power, high speed digital circuits. Adder circuits are broadly employed in all digital computation systems. In this paper, a novel coplanar QCA full adder circuit is proposed which is designed with minimum number of QCA cells. The proposed full adder requires only 13 QCA cells, an area of 0.008 μm² and delay of about 2 clock cycles to implement its function. Then an efficient 4-bit Ripple Carry Adder (RCA) is designed based on the proposed full adder that performs higher end addition in an effective way. Simulations results are obtained precisely using QCA designer tool version 2.0.3. Also the simulation results shows that the proposed 4-bit Ripple Carry Adder (RCA) requires only 70 QCA cells, an area of 0.18 μm² and delay of about 5 clock cycles to implement its function with enhanced performance in terms of latency, area and QCA Cost. From the comparisons, it is found that our work achieves over 55% improvement in QCA cell count.     

A Maximum Time Difference Pipelined Arithmetic Unit Based on CMOS Gate Array

This paper describes a maximum time difference pipelined arithmetic chip,the 36-bit adder and subtractor based on 1.5μm CMOS gate array.The chip can operate at 60MHz,and consumes less than 0.5Watt.The results are also studied,and a more precise model of delay time difference is proposed.     

Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology

This paper focuses on a novel design of an adder/subtractor-based incrementer/decrementer using quantum-dot cellular automata (QCA) technology. QCA is a promising nanotechnology that offers new techniques of computation and data transmission. We use the multilayer crossover technique in the proposed designs to achieve low latency and area for the scalability feature. Moreover, new designs of QCA half and full adders are proposed to improve the operating speed of the incrementer/decrementer. The working of the proposed designs is analyzed via the QCA simulator tool, and the results are compared with previous studies in terms of cell count, area, and latency. According to the analysis, the presented designs perform well; for example, the proposed 4-bit incrementer design shows an improvement of 65 % in terms of area usage and 3.2 times lower latency compared to its existing counterpart.     

Radix-8 full adder in QCA with single clock-zone carry propagation delay

We design a 3-bit adder or a radix-8 full adder (FA) in quantum-dot cellular automata (QCA), where the 3-bit carry propagation path can be accommodated in one clock-zone. To achieve this, we introduce group majority signals similar to group propagate and generate signals in parallel prefix computations, use them to reformulate the carry expressions of a previous radix-4 FA, and as such we could extend it to higher radix FAs. Applying the aforementioned new interpretation of carry expressions (via group majority signals) on 3-bit adders, results in that only a single clock cycle is required for 12-bit (vs. the previous 8-bit) carry propagation, across four radix-8 FAs. Based on the proposed radix-8 QCA-FA, we realized 8-, 16-, 32-, 64, and 128-bit QCA adders via QCADesigner. Comparison of these adders with the previous radix-4 experiment, showed 9–41% speed up, and 57–76% area saving, for 16–128-bit adders, respectively. On the other hand, compared to the best previous radix-2 design, for the same bit widths, we experienced 57–172% speed up, but at the cost of 138–4% area increase, except for the 64 and 128-bit cases, where we also experienced 19% and 41% area saving, respectively.     

VLIW数字信号处理器64位可重构加法器的设计

描述了一款适用于超长指令字数字信号处理器的64位加法器的设计。该加法器高度可重构，可以支持2个64位数据的加法运算、4个32位数据的加法运算、8个16位数据的加法运算以及16个8位数据的加法运算。它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点，使得加法器的面积和连线减少了50%，而延时与加法器的长度的对数成正比。仿真结果表明，在典型工作条件下，采用0.18μm工艺库标准单元，其关键路径的延时为0.83ns，面积为0.149mm2，功耗仅为0.315mW。     

数字信号处理器中高性能可重构加法器设计

设计一款适用于高性能数字信号处理器的16位加法器。该加法器结合条件进位选择和条件“和”选择加法器的特点,支持可重构,可以进行2个16位数据或者4个8位数据的加法运算,同时对其进位链进行优化。相对于传统的条件进位选择加法器,在典型工作条件下,采用0.18μm工艺库标准单元,其延时降低46%,功耗降低5%。     

A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

Multiple-valued quantum logic circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum logic circuits. Adder/subtractor is the major component of the ALU of a computer and is also used in quantum oracles. In this paper, we propose a recursive method of hand synthesis of reversible quaternary full-adder circuit using macro-level quaternary controlled gates built on the top of ion-trap realizable 1-qudit quantum gates and 2-qudit Muthukrishnan–Stroud quantum gates. Based on this quaternary full-adder circuit we propose a reversible circuit realizing quaternary parallel adder/subtractor with look-ahead carry. We also show the way of adapting the quaternary parallel adder/subtractor circuit to an encoded binary parallel adder/subtractor circuit by grouping two qubits together into quaternary qudit values.     

Implementing a one-bit reversible full adder using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technique is one of the emerging and promising nanotechnologies. It has considerable advantages versus CMOS technology in various aspects such as extremely low power dissipation, high operating frequency and small size. In this paper, designing of a one-bit full adder is investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full adder design with reversible QCA1 gates is proposed regarding to overhead and power savings. Our proposed full adder design is more preferable when considering both circuit area and speed. The proposed design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.     

Multi-gate device and summing-circuit co-design robustness studies @ 32-nm technology node

This paper presents a FinFET-based static 1-bit full adder cell that helps to recover the huge penalty in performance, while staying quite close to the minimum energy point. The proposed design offers higher computing speed (by 7.96×) and lower energy (by 5.86×), lower energy-delay product (EDP) (by 21.08×) at the expense of higher power dissipation (by 1.36×) compared to its MOSFET counterpart. It proves its robustness against process variations by featuring tighter spread in power distribution (by 3.20×), in delay distribution (by 4.70×), in PDP (power-delay product) distribution (by 3.35×) and in EDP distribution (by 3.14×) compared to its MOSFET counterpart. The proposed design achieves these improvements due to employment of new FinFET technology in the full adder design. Multi-gate devices in this technology are less affected by random dopant fluctuation (RDF) and short-channel effects such as threshold voltage rolloff, drain-induced barrier lowering (DIBL), etc. To establish that our design is better this paper analyzes five more 1-bit full adder cells and compares them with the proposed design in terms of power, delay and PDP. We perform simulation using 32-nm Predictive Technology Model (PTM) parameters on SPICE.

     

A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis

Quantum-dot cellular automata (QCA) is the appearance of new technology and can be a suitable alternative to semiconductor transistor technology. In this paper, the new structure of the two-input XOR gate is presented, which is the modified version of the three-input XOR gate. This structure can be used to design various useful QCA circuits. By utilizing this gate, we design and implement a new full adder structure with 90-degree cells. This structure is designed in a single layer without cross-wiring. The operation of the proposed structure has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared the effectiveness of our structure with the two previous structures.     

Novel efficient full adder and full subtractor designs in quantum cellular automata

In this study, two new full adder/full subtractor designs based on quantum-dot cellular automata technology have been proposed. By means of the presented equation for SUM and SUBTRACT operations, the new high-speed, low power, and cost efficient designs have been achieved. Even if the three-level design has a lower cell count, occupies less area, and operates at a higher speed, the one-layer design is far more feasible. Analysis of the temperature and energy consumption of the proposed design indicates that the proposed approaches are superior to those of previous works.

     

一种改进的反码加法器设计

传统的加法器在有符号数相加时需将操作数转化为补码形式进行运算,运算结束将计算结果再转化为原码。为减少关键路径延迟,在标志前缀加法器的基础上,提出一种改进的反码加法器,将常用反码加法器中的加一单元合并到加法运算中。在SMIC 0.18 μm工艺下,将改进的64位反码加法器与常用的64位补码加法器进行比较,数据显示面积减少了39.1%,功耗降低了39.9%,关键路径延迟降低了5.1%。结果表明,改进的反码加法器性能较优。     

Area and delay efficient GDI based accuracy configurable adder design

Adders are one of the basic fundamental critical arithmetic circuits in a system and their performances affect the overall performance of the system. Traditional n-bit adders provide precise results, whereas the lower bound of their critical path delay of n bit adder is Ὠ(log n). To achieve a minimum critical path delay lower than Ὠ(log n), many inaccurate adders have been proposed. These inaccurate adders decrease the overall critical path delay and improve the speed of computation by sacrificing the accuracy or predicting the computation results. In this work, a fast reconfigurable approximate ripple carry adder has been proposed using GDI (Gate Diffusion Logic) passing cell. Here, GDI cell acts as a reconfigurable cell to be either connected with the previous carry value or approximated value in an adder chain. This adder has greater advantage and it can be configured as an accurate or inaccurate adder by selecting working mode in GDI cell. The implementation results show that, in the approximate working mode, the proposed 64-bit adder provides up to 23%, 34% and 95% reductions in area, power and delay, respectively compared to those of the existing adder.     

A new construction adder based on Chinese abacus algorithm

A new construction adder based on Chinese abacus algorithm is presented in this paper. There are two kinds of beads used in this construction. Each column element has three higher beads with a weight of four and three lower beads with a weight of one. The proposed 32-bit adder contains eight column elements. The construction was simulated by the technology of TSMC 0.18 μm CMOS process. Layout was also made by the same technology. The maximum delay of the 32-bit abacus adder is 0.91 ns and 14% less than that of Carry Look-ahead Adders for 0.18 μm technology. The power consumption of the abacus adder is 3.1 mW and 28% less than that of Carry Look-ahead Adders for 0.18 μm technology. Recent researches are compared with the proposed adder. The construction was also simulated by Predictive Technology Model. The PTM results also presented. The use of Chinese abacus approach offers a competitive technique with respect to other adders.     

Novel optimized tree-based stack-type architecture for 2n-bit comparator at nanoscale with energy dissipation analysis

Comparator is an essential building block in many digital circuits such as biometric authentication, data sorting, and exponents comparison in floating-point architectures among others. Quantum-dot Cellular Automata (QCA) is a latest nanotechnology that overcomes the drawbacks of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, novel area optimized 2n-bit comparator architecture is proposed. To achieve the objective, 1-bit stack-type and 4-bit tree-based stack-type (TB-ST) comparators are proposed using QCA. Then, two tree-based architectures of 4-bit comparators are arranged in two layers to optimize the number of quantum cells and area of an 8-bit comparator. Thus, this design can be extended to any 2n-bit comparator. Simulation results of 4-bit and 8-bit comparators using QCADesigner 2.0.3 show that there is a significant improvement in the number of quantum cells and area occupancy. The proposed TB-ST 8-bit comparator uses 2.5 clock cycles and 622 quantum cells with area occupancy of 0.49 µm² which is an improvement by 10.5% and 38%, respectively, compared to existing designs. Scaling it to a 32-bit comparator, the proposed architecture requires only 2675 quantum cells in an area of 2.05 µm² with a delay of 3.5 clock cycles, indicating 9.35% and 28.8% improvements, respectively, demonstrating the merit of the proposed architecture. Besides, energy dissipation analysis of the proposed TB-ST 8-bit comparator is simulated on QCADesigner-E tool, indicating average energy dissipation reduction of 17.3% compared to existing works.

     

VLSI中加法器的一种高效自测试设计

基于算术加法测试生成,提出了VLSI中加法器的一种自测试方案:加法器产生自身所需的所有测试矢量.通过优化测试矢量的初值改进这些测试矢量,提高了其故障侦查、定位能力.借助于测试矢量左移、逻辑与操作等方式对加法器自测试进行了设计.对8位、16位、32位行波、超前进位加法器的实验结果表明,该自测试能实现单、双固定型故障的完全测试,其单、双故障定位率分别达到了95.570%,72.656%以上.该自测试方案可实施真速测试且不会降低电路的原有性能,其测试时间与加法器长度无关.     

Delay and area efficient approximate multiplier using reverse carry propagate full adder

The performance and power of error resilient applications will rise with a decrease in designing complexness due to approximate computing. This paper includes the new method for the approximation of multipliers. Variable likelihood terms are produced by the alteration of partial products of the multiplier. Based on the probability statistics, the accumulation of altered partial products leads to the variation of logic complexity. Here the estimate is implemented in 2 variables of 16-bit multiplier and in the final stage with reverse carry propagate adder(RCPA). The reverse carry propagate adder have carry signal propagation from the most significant bit(MSB) to the least significant bit(LSB), which results in greater relevance to the input carry than the output carry. The technique of carry circulation in reverse order with delay variations increases the stability. Utilizing the RCPA in approximate multiplier provide 21% and 7% improvements in area and delay. On comparing, this structure is resilient to delay variations than the ideal approximate adder.     

Design of BCD adder with five input majority gate for QCA

In the digital world BCD numbers play a pivotal role in constituting decimal numbers. New different technologies are emerging in order to obtain low area/power/delay factors to replace the CMOS technology. One such technology is quantum cellular automata (QCA) realization, through which many arithmetic circuits can be designed. This paper deals with the implementation of BCD adder with 5 input majority gates for QCA. The 3 input majority gate and an inverter are basic elements of QCA. In this project amalgamation of majority gates with 3 and 5 inputs are used instead of implementing the entire circuit using 3 input majority gate in the BCD i.e. mainly comprised by partly consumed gates and entirely consumed gates. The proposed is designed and functional verification is done by Verilog HDL and Modelsim version 10.4a. The proposed design has been verified and the delay of existing and proposed design is analysed using Xilinx tool. The numbers of partly consumed and entirely consumed gates are less when compared to the existing method of implementation. The delay is reduced compared to the existing system which shows the improvement of 9.84%. The drawback of crossovers that leads the difficulty in implementation and reduces the efficiency of the circuit is reduced in the proposed implementation.     

面向RSA运算的高速模乘器

根据两位的Booth编码技术和符号预测技术，针对Blakley模乘算法进行了分析和改进，采用了一种理想的适合于硬件实现的算法。根据此算法，并结合CRT算法，实现了一种新的脉动阵列结构，使算法迭代次数减为原来的一半，同时采用高速的大数全加器，大大提高了模乘的运算速度。基于CMOS的0．35m工艺，对于1024位的操作数，可在100Hz时钟频率下工作，完成一次1024位数字签名时间是4．0ms。     

一种用于高速地址产生的32位加法器电路的实现

本文介绍了在某微处理器研制中设计的一种地址生成单元的加法电路。为提高地址转换速度，其进位电路中采用了动态门和多米诺逻辑。结果表明，在1．8v、0．18μm工艺下进行电路模拟，进行一次加法进位传递的时间为466ps。