Plating on acrylonitrile–butadiene–styrene (ABS) plastic: a review

ABS is an engineering plastic that has butadiene part uniformly distributed over the acrylonitrile-styrene matrix. It possesses excellent toughness, good dimensional stability, easy processing ability, chemical resistance, and cheapness. However, it suffers from inherent shortcomings in terms of mechanical strength and vulnerability to environmental conditions. Furthermore, it is non-conducting and easily fretted. Plating on ABS can serve to enhance the strength and structural integrity as well as to improve durability and thermal resistance resulting in metallic properties on the ABS material. ABS is described as the most suitable candidate for plating because it is possible to deposit an adherent metal coating on it by only the use of chemical pretreatment process and without the use of any mechanical abrasion. This article aims to review the history of ABS plastics, properties of ABS, processes and mechanisms of plating, and studies of plating on ABS involving mainly eco-friendly methods of plating by discussing the literature published in recent years. The details of electroplating of ABS carried out in the authors’ laboratory are also presented.     

Sub‐Micron Anisotropic InP‐based III–V Semiconductor Material Deep Etching for On‐Chip Laser Photonics Devices

Two InP‐based III–V semiconductor etching recipes are presented for fabrication of on‐chip laser photonic devices. Using inductively coupled plasma system with a methane free gas chemistry of chlorine and nitrogen at a high substrate temperature of 250 °C, high aspect ratio, anisotropic InP‐based nano‐structures are etched. Scanning electron microscopy images show vertical sidewall profile of 90° ± 3°, with aspect ratio as high as 10. Atomic Force microscopy measures a smooth sidewall roughness root‐mean‐square of 2.60 nm over a 3 × 3 μm scan area. The smallest feature size etched in this work is a nano‐ring with inner diameter of 240 nm. The etching recipe and critical factors such as chamber pressure and the carrier plate effect are discussed. The second recipe is of low temperature (?10 °C) using Cl₂ and BCl₃ chemistry. This recipe is useful for etching large areas of III–V to reveal the underlying substrate. The availability of these two recipes has created a flexible III–V etching platform for fabrication of on‐chip laser photonic devices. As an application example, anisotropic InP‐based waveguides of 3 μm width are fabricated using the Cl₂ and N₂ etch recipe and waveguide loss of 4.5 dB mm^?1 is obtained.

     

Hybrid NSCT domain multiple watermarking for medical images

Multimedia Tools and Applications - Medical image watermarking is a challenging area of research. High bandwidth, secure transmission of patient’s data among hospitals and hiding capacity are...     

Simultaneous tracking and action recognition for single actor human actions

This paper presents an approach to simultaneously tracking the pose and recognizing human actions in a video. This is achieved by combining a Dynamic Bayesian Action Network (DBAN) with 2D body part models. Existing DBAN implementation relies on fairly weak observation features, which affects the recognition accuracy. In this work, we use a 2D body part model for accurate pose alignment, which in turn improves both pose estimate and action recognition accuracy. To compensate for the additional time required for alignment, we use an action entropy-based scheme to determine the minimum number of states to be maintained in each frame while avoiding sample impoverishment. In addition, we also present an approach to automation of the keypose selection task for learning 3D action models from a few annotations. We demonstrate our approach on a hand gesture dataset with 500 action sequences, and we show that compared to DBAN our algorithm achieves 6% improvement in accuracy.     

Visual perception and mixed-initiative interaction for assisted visualization design

This paper describes the integration of perceptual guidelines from human vision with an AI-based mixed-initiative search strategy. The result is a visualization assistant called ViA, a system that collaborates with its users to identify perceptually salient visualizations for large, multidimensional datasets. ViA applies knowledge of low-level human vision to: (1) evaluate the effectiveness of a particular visualization for a given dataset and analysis tasks; and (2) rapidly direct its search towards new visualizations that are most likely to offer improvements over those seen to date. Context, domain expertise, and a high-level understanding of a dataset are critical to identifying effective visualizations. We apply a mixed-initiative strategy that allows ViA and its users to share their different strengths and continually improve ViA's understanding of a user's preferences. We visualize historical weather conditions to compare ViA's search strategy to exhaustive analysis, simulated annealing, and reactive tabu search, and to measure the improvement provided by mixed-initiative interaction. We also visualize intelligent agents competing in a simulated online auction to evaluate ViA's perceptual guidelines. Results from each study are positive, suggesting that ViA can construct high-quality visualizations for a range of real-world datasets.     

Reducing the overhead of dynamic compilation

The execution model for mobile, dynamically‐linked, object‐oriented programs has evolved from fast interpretation to a mix of interpreted and dynamically compiled execution. The primary motivation for dynamic compilation is that compiled code executes significantly faster than interpreted code. However, dynamic compilation, which is performed while the application is running, introduces execution delay. In this paper we present two dynamic compilation techniques that enable high performance execution while reducing the effect of this compilation overhead. These techniques can be classified as (1) decreasing the amount of compilation performed, and (2) overlapping compilation with execution. We first present and evaluate lazy compilation, an approach used in most dynamic compilation systems in which individual methods are compiled on‐demand upon their first invocation. This is in contrast to eager compilation, in which all methods in a class are compiled when a new class is loaded. In this work, we describe our experience with eager compilation, as well as the implementation and transition to lazy compilation. We empirically detail the effectiveness of this decision. Our experimental results using the SpecJVM Java benchmarks and the Jalapeño JVM show that, compared to eager compilation, lazy compilation results in 57% fewer methods being compiled and reductions in total time of 14 to 26%. Total time in this context is compilation plus execution time. Next, we present profile‐driven, background compilation, a technique that augments lazy compilation by using idle cycles in multiprocessor systems to overlap compilation with application execution. With this approach, compilation occurs on a thread separate from that of application threads so as to reduce intermittent, and possibly substantial, delay in execution. Profile information is used to prioritize methods as candidates for background compilation. Methods are compiled according to this priority scheme so that performance‐critical methods are invoked using optimized code as soon as possible. Our results indicate that background compilation can achieve the performance of off‐line compiled applications and masks almost all compilation overhead. We show significant reductions in total time of 14 to 71% over lazy compilation. Copyright © 2001 John Wiley & Sons, Ltd.     

A comparative study of GPU programming models and architectures using neural networks

Recently, General Purpose Graphical Processing Units (GP-GPUs) have been identified as an intriguing technology to accelerate numerous data-parallel algorithms. Several GPU architectures and programming models are beginning to emerge and establish their niche in the High-Performance Computing (HPC) community. New massively parallel architectures such as the Nvidia??s Fermi and AMD/ATi??s Radeon pack tremendous computing power in their large number of multiprocessors. Their performance is unleashed using one of the two GP-GPU programming models: Compute Unified Device Architecture (CUDA) and Open Computing Language (OpenCL). Both of them offer constructs and features that have direct bearing on the application runtime performance. In this paper, we compare the two GP-GPU architectures and the two programming models using a two-level character recognition network. The two-level network is developed using four different Spiking Neural Network (SNN) models, each with different ratios of computation-to-communication requirements. To compare the architectures, we have chosen the two extremes of the SNN models for implementation of the aforementioned two-level network. An architectural performance comparison of the SNN application running on Nvidia??s Fermi and AMD/ATi??s Radeon is done using the OpenCL programming model exhausting all of the optimization strategies plausible for the two architectures. To compare the programming models, we implement the two-level network on Nvidia??s Tesla C2050 based on the Fermi architecture. We present a hierarchy of implementations, where we successively add optimization techniques associated with the two programming models. We then compare the two programming models at these different levels of implementation and also present the effect of the network size (problem size) on the performance. We report significant application speed-up, as high as 1095× for the most computation intensive SNN neuron model, against a serial implementation on the Intel Core 2 Quad host. A comprehensive study presented in this paper establishes connections between programming models, architectures and applications.     

The Role of the Prefrontal Cortex in the Maintenance of Verbal Working Memory: An Event-Related fMRI Analysis.

Neuroimaging studies have been inconclusive in characterizing the role of the prefrontal cortex (PFC) for maintaining increasingly larger amounts of information in working memory (WM). To address this question, the authors collected event-related functional MRI data while participants performed an item-recognition task in which the number of to-be-remembered letters was parametrically modulated. During maintenance of information in WM, the dorsolateral and the ventrolateral PFC exhibited linearly increasing activation in response to increasing WM load. Prefrontal regions could not be distinguished from one another on the basis of load sensitivity, but the dorsolateral PFC had stronger functional connectivity with the parietal and motor cortex than the ventrolateral PFC. These results suggest an increasingly important role for the PFC in actively maintaining information as the amount of that information increases. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

A study on fitness-for-service assessment for crack-like defects and corrosion in nuclear reactor pressure tubes

This paper looks forward to thoroughly assess zirconium alloy (Zr-2) pressure tubes used in nuclear power reactors for crack like and corrosion type defects. It emphasizes on the use of reliability concept for determining the probability of failure of zirconium alloy pressure tubes based on deuterium ingress. The in depth analysis carried out to calculate the reliability index for the above two problems is based on FORM approach. A steady state corrosion rate is assumed to estimate the growth in the dimensions of corrosion defects. The methodology suggested in this paper is useful for designers and plant engineers in timely detection of the cracks and leaks in the pressure tubes used in nuclear reactors and initiate suitable corrective actions based on their criticality.     

Design of robust model-based controllers via parametric programming

In this paper a method is presented for deriving the explicit robust model-based optimal control law for constrained linear dynamic systems. The controller is derived off-line via parametric programming before any actual process implementation takes place. The proposed control scheme guarantees feasible operation in the presence of bounded input uncertainties by (i) explicitly incorporating in the controller design stage a set of feasibility constraints and (ii) minimizing the nominal performance, or the expectation of the performance over the uncertainty space. An extension of the method to problems involving target point tracking in the presence of persistent disturbances is also discussed. The general concept is illustrated with two examples.