基于关键路径的三模冗余表决器插入算法

在FPGA的三模冗余设计中,寄存器的反馈环路会导致错误持续出现,严重影响三模冗余的容错性能,因此需要在寄存器的反馈环路上插入表决器。该文首次提出了一种针对映射后网表进行三模冗余设计的方法,同时提出了基于关键路径的表决器插入算法,该算法在表决器的插入时避开关键路径,缓解了三模冗余设计中插入表决器时增加延时的影响。与国外同类算法相比,该文算法在不降低电路可靠性的前提下,以不到1%的面积开销,使得关键路径延时减少3%~10%,同时算法运算速度平均提高35.4%。     

Short communication: Feeding method affects the feeding behavior of growing dairy heifers

There is limited information available on what is the most appropriate feeding method for growing dairy heifers. The objective of this study was to determine the effect of feeding method on the feeding behavior and diet selection of growing dairy heifers. Six prepubescent Holstein heifers (158.2 ± 4.0 d old, weighing 168.2 ± 15.7 kg), fed once per day for 1.0 kg/d of growth, were subjected to each of 3 treatments in 3 successive 7-d treatment periods using a replicated 3 × 3 Latin square design. Treatments consisted of feeding 2.02 kg/d dry matter of grain concentrate and ad libitum chopped grass hay as: 1) choice (grain concentrate and hay in separate feed bins), 2) top-dressed ration (grain concentrate placed on top of the hay in one feed bin), and 3) total mixed ration (TMR, grain concentrate mixed with hay in one feed bin). Dry matter intake (DMI) and feeding behavior were monitored for 7 d for each animal on each treatment, and feed sorting was monitored for the last 3 d of each treatment period. The provision of grain concentrate and hay in either a choice or top-dressed situation resulted in young dairy heifers rapidly consuming the grain concentrate portion of their ration in very few, large meals before consuming the hay portion of their ration. The provision of the 2 ration ingredients as a TMR increased the distribution of DMI over the day and reduced the amount of sorting (against long forage particles, and for short grain concentrate particles) by heifers. These results suggest that the provision of a TMR to growing dairy heifers, as opposed to feeding concentrate and hay as either a choice or top-dressed, promotes a more balanced intake of nutrients across the day.     

压缩机综合控制系统在催化裂化装置中的应用

原催化裂化装置主风机组控制仪表严重落后老化,控制系统可靠性降低,不适应新的联锁自保及机组控制的安全标准和要求。经升级改造,新的机组控制系统采用了压缩机综合控制系统（ITCC）,控制器为经过安全认证的三重化冗余（TMR）Tricon控制器,轴流压缩机防喘振控制采用专用的防喘振控制和调速及性能控制软件,提高了机组控制系统的安全性、可靠性,使操作调节更加简便。     

HFFQ9HLP-8全混日粮粮搅拌车绞龙设计

全混日粮搅拌车要用于奶牛、肉牛全混合日粮（TMR）加工制作的专用设备,能够将各种精、粗饲料按照一定的配方比例混合搅拌均匀,提高饲料的适口性和营养的均衡性。绞龙是其重要工作部件。为此,应用CAD和UG NX对绞龙进行辅助设计,对绞龙强度进行有限元分析,以提高TMR饲料搅拌车绞龙性能,减少物料残留。     

广义TMR码的设计

本文推导了确定广义ＴＭＲ码截短距离ｄ（ｃ｜１）的一种算法，从而提供了字节长为任意的广义ＴＭＲ码的通用设计方法。     

TMR计算机系统分布与容错工作方式间的切换

ＦＴ－ＨＩＴ是我们自行研制的三模冗余航天容错计算机。系统采用硬件三模冗余结构和主要由软件实现容错的冗余管理模式，具有容错计算和分布处理两种工作方式，保证了航天容错计算机的高可靠性和强大的处理能力。本文主要论述其容错和分布两种工作方式间的切换机理并给出具体的实现算法，算法对于一     

基于Nand Flash的星载综合数据固态记录系统

在星载平台资源受限条件下,采用以FPGA+CPU为控制核心、Nand Flash为固态存储阵列的系统架构,实现了高速、大容量、高可靠的数据记录.针对传统双Plane操作与并行扩展对存储速度提升有限、芯片使用较多的问题,采用4级流水线方式控制Flash阵列.为解决标准传输协议传输效率低的问题,设计了一种自定义高速串行传输协议.为减缓空间辐射环境对存储数据的影响,采用了三模冗余、配置回读与部分重构等容错机制.对所提出系统进行的实验验证结果表明,该星载记录系统存储容量达36 Tbit,记录与回放速度分别达到16 Gbit/s与8 Gbit/s,传输误码率为10-12,传输包效率为96.7％,可作为通用存储系统以满足航天应用需求.     

基于TMR旁路代自动化处理解决方案

结合湖北某电力公司TMR现场实际运行情况,设计并实现了一套基于旁路代的自动处理旁路代电量计算的系统,大大提高了电能量计量系统的实用化程度和旁路自动化管理水平。     

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Heavy ion experiments were performed on D flip-flop （DFF） and TMR flip-flop （TMRFF） fabricated in a 65-nm bulk CMOS process. The experiment results show that TMRFF has about 92% decrease in SEU cross- section compared to the standard DFF design in static test mode. In dynamic test mode, TMRFF shows much stronger frequency dependency than the DFF design, which reduces its advantage over DFF at higher operation frequency. At 160 MHz, the TMRFF is only 3.2~ harder than the standard DFF. Such small improvement in the SEU performance of the TMR design may warrant reconsideration for its use in hardening design.     

一种应用于SpaceWire路由器动态部分重构的容错技术

为满足航天器有效载荷间高速数据多路传输未来发展和空间抗辐射的需求,研究了一种应用于SpaceWire路由器动态部分重构的容错技术。在SpaceWire总线标准网络层分析的基础上,对cell矩阵无阻塞路由增添HanMing编码实现纠一检二,当检测出大于一个错误不能纠正时,采用局部重构的方式对有误的单个cell单元进行三重冗余重构,同时采用Partition Pin来代替传统的总线宏作为静态模块和动态模块的传输枢纽,并对容错前后路由器的资源和延时时间进行了评估和比较。实验结果表明,比将整个路由cell矩阵三模冗余,该方法能够节约硬件资源和减少延迟时间。