Post-deposition heat treatment of co-deposited Cr3C2 and AISI 410 stainless steel using the coaxial laser deposition technique

Cr₃C₂ ceramic powder is added in varying amounts to AISI 410 stainless steel powder to develop AISI 400 based alloys with varying chromium and carbon content using the coaxial laser deposition technique operating at parameter sets which guarantee full melting of the constituent powder particles. Theoretical isothermal curves for the in situ generated alloys are correlated with the as-deposited and heat-treated microstructures using electron microscopy, X-ray and electron backscatter diffraction techniques. It is concluded that with an increased carbon loading in the mixture, post-deposition heat treatment involving full re-austenitising and tempering is necessary in order to reduce the effect of solute trapping which negatively affects the material mechanical properties.     

CMOS implementation of a 1.6 GHz low voltage low phase noise quadrature output frequency synthesizer with automatic amplitude control

This article presents the design of a 1.2 V CMOS low phase noise quadrature output frequency synthesizer (FS) to be used for a GPS tuner application. Special reference is made to the design of a wide tuning range quadrature output voltage-controlled oscillator which is equipped with an automatic amplitude controller. It exhibits a phase noise response of less than −115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 36%. The effect of the automatic amplitude control is shown to improve phase noise at high oscillation frequencies and its noise has a negligible effect on the phase noise response even at low offset frequencies from the carrier. Preliminary analysis is presented showing the negligible effect of a DC–DC converter on the spurious level of the FS, included to permit the use of low sensitivity varactors. Design guidelines for reducing both the loop noise and the AM-to-PM conversion factors of the oscillator are also given. The design was made using the STMicroelectronics 0.13 μm HCMOS9-RF technology design kit.     

Room-temperature, monolithic, electrically-pumped type-L quantum-well SB-based VCSELS emitting at 2.3 mm

An all-epitaxial monolithic vertical cavity surface emitting laser grown on GaSb substrate is presented. The structure is composed of two n-doped AlAsSb/GaSb distributed Bragg reflectors, a type-I GalnAsSb/AlGaAsSb multi-quantum-well active region and a tunnel junction. Quasi continuous-wave laser operation is demonstrated at 2.3 mum up to room temperature. Threshold current densities of 0.8 and 0.6 kA/cm^-2 are obtained at 300 and 280 K for 80 mum-diameter devices (1 mus pulses, 10% duty cycle). A peak output optical power of 2 mW was achieved at 280 K.     

A 1 V Second Order Sigma-Delta Modulator

A second order switched capacitor sigma-delta modulator operating at a supplyvoltage of 1 V is presented. This low supply voltage restricts the gate overdrivevoltage available for switching transistors. The design relies on the elimination ofcritical switches by using a modified switched op amp for the integrator and novelswitched half-supply and reference voltage generators. The design has been carried outin a fully differential configuration in order to minimize errors arising from chargeinjection and clock-feedthrough effects. The converter has been implemented using aconventional 0.8 m double-poly double-metal CMOS process, having a nominalthreshold voltage of 0.75 V. Test results, showing more than 9 bits of resolutionwith an oversampling ratio of 64, are also presented.     

The analysis of warpage in wafer-level compression molding

Advanced 3D MEMS packaging technologies involving the encapsulation of devices at wafer-level are being developed in order to achieve further minimization and cost reduction of consumer electronic devices. Compression molding using epoxy molding compounds is one technique being considered for wafer-level encapsulation. Excessive out-of-plane deformation has been reported in wafer-level compression molding trials using blank wafers which would negatively impact device reliability and the implementation of successive processes to the molded wafer. This paper presents finite element models of the molded wafer, with and without embedded dies which simulate the observed multi-state warpage characteristics. Molded wafer warpage measurements were also carried out in order to verify the applicability of the small and large deformation theories for layered plates and to verify the finite element model of the molded blank wafer. Possible factors (non-planar mold layer thickness and anisotropic wafer elastic properties) leading to asymmetric warpage in molded blank wafers were also investigated. From the molded wafer model with embedded dies the effects of flip-chip die dimensions and wafer thickness on the out-of-plane deformation together with possible reliability issues were analyzed.

     

±0.9 V switched-capacitor CMOS multiplier with rail-to-railinput

An analogue, fully differential, switched capacitor CMOS multiplier with rail-to-rail input capability is presented, together with simulation results. The multiplier can operate at a clock frequency of 10 MHz when operated from a ±0.9 V power supply. Special attention has been given to the minimisation of clock feedthrough errors and also to achieve a low common mode voltage error at the output. The latter makes the device suitable for use in correlators with large integration periods