DRIE工艺误差对MEMS梳齿谐振器频率的影响

针对深反应离子刻蚀(DRIE)工艺加工高深宽比梳齿电容存在侧壁倾斜角的情况,分析了该倾斜角对梳齿谐振器频率的影响。为了使设计的梳齿谐振器频率符合应用要求,推导出了梳齿谐振器在正负侧壁倾斜角θ下的谐振频率计算公式。利用ANSYS Workbench11.0平台,分别对侧壁倾斜角为0°,0.2°,0.35°和0.5°的情形进行了有限元建模与模态仿真。仿真结果表明:随着正倾斜角的增大,谐振频率减小;负倾斜角增大时,谐振频率增大,且一阶模态振形的平稳程度越差。比较数值仿真结果与考虑了正负倾斜角误差的梳齿谐振器谐振频率计算公式计算结果对比,吻合较好。     

基于双面盲孔电镀的硅通孔工艺研究

针对当前微机电系统(MEMS)发展对小型化封装的需求,设计了一种高可靠性、低成本、高深宽比的硅通孔(TSV)结构工艺流程。该工艺流程的核心是双面盲孔电镀,将TSV结构的金属填充分为正、反两次填充,最后获得了深度为155 μm、直径为41 μm的TSV结构。使用功率器件分析仪对TSV结构的电学性能进行了测试,使用X光检测机和扫描电子显微镜(SEM)分别观察了TSV结构内部的缺陷分布和填充情况。测试结果证明,TSV样品导电性能良好,电阻值约为1.79×10-3 Ω,孔内完全填充,没有空洞。该研究为实现MEMS的小型化封装提供了一种解决方法。     

硅DRIE刻蚀工艺模拟研究

随着现代科技的发展,人们对微系统的小型化、高性能、多功能、低功耗和低成本的要求越来越高,基于硅通孔技术技术的三维系统封装技术(3D SiP,three dimensional dystem in packaging)愈发显现出其重要的研究价值.硅通孔技术将集成电路垂直堆叠,在更小的面积上大幅地提升芯片性能并增加芯片功能...     

DRIE技术加工W波段行波管折叠波导慢波结构的研究

简要介绍了利用深反应离子刻蚀制作折叠波导慢波结构的现状及制作的工艺流程。对深反应离子刻蚀掩膜制作即光刻工艺,以及折叠波导慢波结构的深刻加工进行了深入的研究。详细分析了各光刻工艺对光刻胶图形的影响,尤其是前烘对光刻胶图像侧壁垂直度的影响;在深反应离子刻蚀中,还详细分析了刻蚀时间、下电极功率以及刻蚀气体气压对刻蚀结果的影响。经参数优化后获得最佳工艺参数,并制作出带有电子注通道的W波段折叠波导慢波结构,慢波结构深为946μm,侧壁垂直度为91°,电子注通道深为225μm,侧壁垂直度为90°。     

Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget

We report on a top-down complementary metal oxide semiconductor (CMOS) compatible fabrication method of ultra-high density Si nanowire (SiNW) arrays using a time multiplexed alternating process (TMAP) with low temperature budget. The flexibility of the fabrication methodology is demonstrated for curved and straight SiNW arrays with different shapes and levels. Ultra-high density SiNW arrays with round or rhombic cross-sections diameters as low as 10 nm are demonstrated for vertical and horizontal spacing of 60 nm. The uniqueness of the technique, which achieves several advantages such as bulk-Si processing, low-thermal budget, and wide process window makes this fabrication method suitable for a very broad range of applications such as nano-electro-mechanical systems (NEMS), nano-electronics and bio-sensing.     

Substrate interconnect technologies for 3-D MEMS packaging

We report the development of 3-dimensional silicon substrate interconnect technologies, specifically for reducing the package size of a MOSFET relay. The ability to interconnect multiple chips at different elevations on a single substrate can significantly improve device performance and size. We present the process development of through-hole interconnects fabricated using deep reactive ion etching (DRIE), with an emphasis on achieving positively tapered, smooth sidewalls to ease deposition of a seed layer for subsequent Cu electroplating. Gray-scale technology is integrated on the same substrate to provide smooth inclined surfaces between multiple vertical levels (>100 μm apart), enabling interconnection between the two levels via simple metal evaporation and lithography. The developments discussed for each technique may be used together or independently to address future packaging and integration needs.     

一种用于硅基MEMS加工的深刻蚀技术

研究了光辅助电化学刻蚀技术，并特别研究了阵列和硅衬底之间的边缘效应。在阵列边缘由于电流分布不均匀以及空穴从孔的侧壁注入，因此可以在边缘区域观察到结构的坍塌，采用一个周期性变化的信号来调制光照的强度，边缘效应会得到一定的抑制。同时，也观察到了硅的电化学深刻蚀工艺中大电流情况下的抛光现象（阳极氧化条件下，硅表面在氢氟酸溶液中快速均匀溶解不形成孔的现象）。光学测试表明，制作的正方格子结构具有光予晶体行为，其光学禁带位于6μm附近。     

基于体硅工艺的定位平台制作工艺分析研究

介绍了一种基于体硅工艺的大尺寸、大深宽比的纳米级定位平台的制作工艺。对定位平台的制作中的关键工艺进行的分析，总结了导致器件失效的主要原因，探讨了减少失效的方法。同时介绍了一种可行的面内侧面压阻的加工方法。通过对深度反应离子刻蚀（DRIE）工艺参数的调整成功了刻蚀出了大尺寸、大深宽比的结构释放窗口，释放了最小线宽为2.5μm，厚度为50微米的梳齿结构。研制了一种良好性能的集成位移检测的纳米级定位平台。     

A systematic study of DRIE process for high aspect ratio microstructuring

Various MEMS devices like Accelerometers, Resonators, RF- Filters, Micropumps, Microvalves, Microdispensers and Microthrusters are produced by removing the bulk of the substrate materials. Fabrications of such Microsystems requires the ability to engineer precise three-dimensional structures in the silicon substrate. Fabrication of MEMS faces multiple technological challenges before it can become a commercially viable technology. One key fabrication process required is the deep silicon etching for forming high aspect ratio structures. There is an increasing interest in the use of dry plasma etching for this application because of its anisotropic etching behavior, high etch speed, good uniformity and profile control, high aspect ratio capabilities without having any undesired secondary effects i.e. RIE lags, Loading, microloading, loosing of anisotropic nature of etching as aspect ratio increases, micro-grass and even etch stalling. Developing a DRIE micro-machining process requires a thorough understanding of all plasma parameters, which can affect a silicon etching process and their use to suppress the secondary effects. In this paper our intention is to investigate the influence of etching gas flow, etching gas pressure, passivation gas pressure, ICP coil power, Platen power and etch and passivation time sequence on etch rate and side wall profile. Parameter ramping is a powerful technique used to achieve the requirements of high aspect ratio microstructures (HARMS) for MEMS applications by having high etch rate with good profile/CD control. The results presented here can be used to rationally vary processing parameters in order to meet the microstructural requirements for a particular application.     

负载刚度对电热微执行器输出性能的影响分析

针对微机电系统中电热微执行器和位移放大机构都具有柔性的事实,从理论上分析了作为负载系统的柔性位移放大机构对微执行器输出位移的影响,并用有限元方法对二者的工作性能进行了仿真.结果表明,电热微执行器外接负载的刚度和执行器本身刚度的比值是影响整个组合器件性能的重要因素.最后用深层反应离子刻蚀技术(DRIE)在硅隔离衬底(SOI)上加工了电热微执行器和柔性位移放大机构,并对其进行了测试,测试结果与有限元分析结果符合得很好.