高深宽比深隔离槽的刻蚀技术研究

体硅集成MEMS器件中的一个非常重要的技术就是微结构与电路部分的电隔离和互连。由于体硅工艺与传统CMOS工艺不兼容 ,所以形成高深宽比的深隔离槽 (宽约 3μm ,深 2 0～ 10 0μm)是体硅集成中急待解决的工艺难题。本文采用MEMS微加工的DRIE (DeepReactiveIonEtching)技术、热氧化技术和多晶硅填充技术 ,形成了高深宽比的深电隔离槽 (宽 3.6 μm ,深 85μm)。还提出了一种改变深槽形状的方法 ,使深槽的开口变大 ,以利于多晶硅的填充 ,避免了空洞的产生     

用于高产量MEMS以及3D互联技术的低成本深层反应离子刻蚀系统(英文)

新兴的 3D 互联技术以及高产量的 MEMS 应用需要成本低廉以及高产量的深层反应离子刻蚀系统。最优化的 Alcatel 深层反应离子刻蚀系统可以同时满足工艺以及硬件生产性能的高要求。这些都已经在典型刻蚀工艺上进行了研究, 包括斜面刻蚀、堆叠时的 CMOS 刻蚀侧壁角度、3D 高精度惯性传感器的良好控制的形貌、大面积刻蚀的打印机喷头和硅麦克风应用。优化的工艺参数意味着在刻蚀率, 刻蚀的深宽比, notch free 的工艺, 光滑度以及高精度控制各方面的显著提高。Alcatel AMS 200 “I-Productivity”DRIE 机台用于高产量的工艺同时也确保了生产参数如整机效率的提高以及使用成本的降低, 这是通过机台的无可替代的硬件以及工艺方案实现的。     

一种新结构硅微机械压阻加速度计

设计、制造并测试了一种新结构硅微机械压阻加速度计.器件结构是悬臂梁-质量块结构的一种变形.比较硬的主悬臂梁提供了一定的机械强度,并且提供了高谐振频率.微梁很细,检测时微梁沿轴向直拉直压.力敏电阻就扩散在微梁上,质量块很小的挠动就能在微梁上产生很大的应力,输出很大的信号.5 V条件下,灵敏度为14.80 mV/g,谐振频率为994 Hz,分别是传统结构压阻加速度计的2.487倍和2.485倍.加速度计用普通的N型硅片制造,为了刻蚀高深宽比的结构,使用了深反应离子刻蚀(DRIE)工艺.     

Fabrication of a Thermally Isolated and Pre-Amplified Transistor Module with Polyimide Micro-Wires for Cryogenic Detectors

We report a pre-amplifying junction field effect transistor (JFET) module on a chip for cryogenic applications such as bolometer and X-ray microcalorimeter. In order to maintain the optimum performance of the JFETs at 130 K, the module has built-in aluminum micro-heaters while the JFETs are thermally isolated from a heat sink. The thermal isolation is achieved by suspending a micromachined silicon support platform (6 μm thick) with polyimide wires. A layer of aluminum electrodes is patterned on top of the polyimide wires for electrical contacts and on top of the silicon platform for the heaters. This process involves reactive-ion-etching (RIE) of silicon and polyimide, patterning of aluminum electrodes over the polyimide, back side deep-reactive-ion-etching (DRIE) of silicon, and releasing of the modules. In this paper, we describe a micromachining process of the JFET modules on silicon-on-insulator (SOI) wafers.      

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

A wide range of requests coming from customer appears to demonstrate the feasibility of the TSV for a large range of via size and via AR either for process point of view or for performances point of view. The main application in the market is the CMOS image sensor with the integration of via at AR1. Now based on this first wafer level package of CMOS Image Sensor (CIS), the integration on the z axe will continue by the wafer lens integration for a continuous form factor and low cost module.First 3Di applications with TSV is entering the market with the via-last approach, more simply to be developed in semiconductor manufacturing in order to secure the 3Di technologies and to promote the 3Di to customers. Then specific design and electrical models will be developed and optimized allowing a fast and prosperous development of the via-first approach.A challenge in the modelisation of the TSV is the understanding of the mechanical impact of the trench and the metal filling on the behavior of the CMOS components and the reliability. These types of researches are progressing in various institutes and are essential for an increasing integration of TSV.Because actually, the technology continues to drive the 3D roadmap, the mechanical and thermal modelisation and 3D design tool need to be more activated to be developed faster in order to optimize the 3D module. Then the electrical testing will be a real challenge to be able to distinguish drift in the right strata, to be able to isolate a via within more than 10000 via in a module. The electrical testing will be strictly linked to mechanical and electrical failure analysis to get feed-back in technology, actual drawback of the 3D development.The cost of the 3Di and the TSV integration is more and more important and looks as a primary driver even if the functionalities increase faster than cost! Some steps have been already identified to be more costly steps: bonding and via filling. Indeed, throughput and material used have a direct impact on the final price.Continuous perspectives of TSV integration are progressing in order to optimise actual applications or to develop new integration. First challenging integration is the interposers with 3D interconnection allowing devices mounting on both side, like passive device integration or building of micro-cooling channels. The main interest of the 3D silicon interposer is the fact that it can connect chips at different locations and sizes, as example memory over digital IC. The usage of silicon as an interposer leads to an increase in the cost, but it will boost performances and reduce power consumption. One other advantage of the introduction of 3D interposer is the simplification of the required substrate implying a better mismatch of CTE lowering the packaging failure.In the wafer level package, TSV is now introduced to reduce the package footprint and mainly simplify the capping of device, similar to that for the MEMS. Indeed by integrating TSV, the capping must only protect the device against external environment, and not also take into account the electrical path in the bond layer degrading the hermiticity performance.To finish this paper, the sentence of Yann Guillou is the right situation: “The (3D) roadmaps need to be based on application requirements and not driven by technology ONLY. 3D Integration with TSV is not a scaling based concept Does it make sense today to think about submicron via diameter or dice thinner than 30 μm for example?” Applications need to take a risk by using 3D TSV technology!     

高深宽比硅通孔检测技术研究

由于SEM显微镜、FIB显微镜检测高深宽比硅通孔耗时、费用高,研究了垂直扫描白光干涉技术检测硅通孔的可行性。设定刻蚀/钝化时间比率,改变深硅刻蚀功率和刻蚀时间,获得不同深度和侧壁粗糙度的硅通孔,并用垂直扫描白光干涉技术进行检测。研究结果表明垂直扫描白光干涉技术可以观察硅通孔的形状、测量侧壁粗糙度、精确无损测量硅通孔深度,可以替代SEM、FIB检测方法。     

转动竖直镜面的微机械光开关

提出并制作了转动竖直微镜的微机械光开关,采用曲线形状的电极设计,有效地减低了悬臂梁驱动器的吸合电压,采用体硅深刻蚀技术结合(110)硅的各向异性腐蚀技术制备了光开关芯片和耦合对准的U形槽和卡簧。芯片经初步封装后进行了电学测试和光学测试,测得吸合电压78.5V,谐振频率2.3kHz,光开关损耗5dB,隔离度45dB。     

Bulk micromachining fabrication platform using the integration of DRIE and wet anisotropic etching

This study presents a bulk micromachining fabrication platform on the (100) single crystal silicon substrate. The fabrication platform has employed the concept of vertical corner compensation structure and protecting structure to integrate the wet anisotropic etching and DRIE processes. Based on the characteristics of wet anisotropic etching and DRIE, various MEMS components are demonstrated using the bulk micromachining platform. For instance, the free suspended thin film structures and inclined structures formed by the {111} crystal planes are fabricated by the wet etching. On the other hand, the mesas and cavities with arbitrary shapes and the structures with different leve l heights (or depths) are realized by the characteristics of DRIE. Since the aforementioned structures can be fabricated and integrated using the presented fabrication platform, the applications of the bulk micromachining processes will significantly increase.This research is based on the work supported by WALSIN LIHWA Corporation and the National Science Council of Taiwan under grant of NSC-91–2218-E-007–034. The authors would like to thank the Central Regional MEMS Research Center of National Science Council, Semiconductor Research Center of National Chiao Tung University and National Nano Device Laboratory for providing the fabrication facilities.     

MEMS硅膜电容式气象压力传感器的研制

基于MEMS的电容式压力传感器以其低成本高性能在气象测量中有着广阔的应用前景。利用ANSYS软件模拟接触式电容压力传感器的工作状态，得到硅膜的形变和应力分布状况。制作流程采用简单标准的工艺：利用KOH各向异性腐蚀进行硅片大面积、大深度腐蚀减薄，分析了其浓度配比对硅面平整度特性的影响，采用阳极键合形成真空腔，试验反应离子深刻蚀形成硅膜的效果。芯片测试结果表明方案可行。     

Advances in piezoelectric thin films for acoustic biosensors,acoustofluidics and lab-on-chip applications

Recently, piezoelectric thin films including zinc oxide (ZnO) and aluminium nitride (AlN) have found a broad range of lab-on-chip applications such as biosensing, particle/cell concentrating, sorting/patterning, pumping, mixing, nebulisation and jetting. Integrated acoustic wave sensing/microfluidic devices have been fabricated by depositing these piezoelectric films onto a number of substrates such as silicon, ceramics, diamond, quartz, glass, and more recently also polymer, metallic foils and bendable glass/silicon for making flexible devices. Such thin film acoustic wave devices have great potential for implementing integrated, disposable, or bendable/flexible lab-on-a-chip devices into various sensing and actuating applications. This paper discusses the recent development in engineering high performance piezoelectric thin films, and highlights the critical issues such as film deposition, MEMS processing techniques, control of deposition/processing parametres, film texture, doping, dispersion effects, film stress, multilayer design, electrode materials/designs and substrate selections. Finally, advances in using thin film devices for lab-on-chip applications are summarised and future development trends are identified.