电压对电刷镀三价铬镀层性能的影响

在45钢表面电刷镀得到三价铬镀层,镀液组成和工艺条件为:Cr2(SO4)36H2O 0.4 mol/L,甲酸铵0.5 mol/L,氨基乙酸0.5 mol/L,H3BO30.6 mol/L,NaH2PO2 H2O 0.3 mol/L,pH=1.5,温度50°C,镀笔移动速率15 cm/s。研究了电压对镀铬层显微结构、表面粗糙度、厚度、显微硬度和耐磨性的影响。随电压增大,镀层厚度增大,显微硬度和耐磨性均先提高后降低。电压为14 V时,镀层的表面平整,粗糙度为2.387μm,显微硬度为602 HV,耐磨性最好。     

A directional control method for interface flow considering static voltage stability

A directional control method (DCM) for power flows on a set of interface lines between two regions of power system considering static voltage stability margin is developed in this paper. A surface approximation approach is firstly used to obtain the relationship between the interface flow solution and the generation direction of generator (the portion of generation variation in each participating generator to satisfy the desired power increase on the interface and the system loss). Then, an optimization model is built to determine the optimum dispatching scheme of generators. This method not only can control the total power on the interface to satisfy the power demand but also can realize the directional control of power on each interface line based on the needs of operation. The proposed DCM is further extended to determine the optimum dispatching scheme of generators for maximizing the interface flow margin (IFM), which is the active power margin of the key transmission lines between two regions of power system constrained by static voltage stability. A modified continuation power flow (MCPF) is used to show and evaluate the impacts of the DCM on the IFM. The New England 39-bus system and the IEEE 300-bus system have been employed to verify the effectiveness of the DCM.     

中高压变频器冷却方案比较和选型分析

随着电力电子器件的发展,性能优异的中高压变频器在各行各业中得到越来越广泛的应用,能否处理好变频器的散热问题是其长期稳定运行的关键。分析了中高压变频器热量产生来源,并从技术可行性、可靠性、经济性等角度对不同冷却方案的特点进行比较,并结合实际的工程案例,给出合理的变频器冷却方案选型建议,可作为工程电气设计时中高压变频器冷却方案选型参考。     

Application of differential evolution for cascaded multilevel VSI with harmonics elimination PWM switching

Harmonic elimination pulse width modulation (HEPWM) method has been widely applied to multilevel voltage source inverter (MVSI) to remove low frequency harmonics from its output voltage. However, the computation of the HEPWM switching angles for MVSI is very challenging due to several constraints, namely angle sequencing, very tight angular spacing and the numerous possibilities of angles distribution ratio. Realizing the potential of Differential Evolution (DE) to handle complex problems, this work proposes its application to solve the HEPWM problem for cascaded MVSI. Its emphasis is on improving the availability of HEPWM for higher output voltage by extending the maximum range of modulation index (M). It also removes the discontinuities in the switching angles and reduces the number of distribution ratio required to obtain the required solution. Compared to the most advanced (similar) work, i.e., 7-level MVSI with seventeen switching angles, DE covers a wider range of M; the maximum achievable M is 2.80. Furthermore, it exhibits very low second order distortion factor (DF₂): for the worst case, the value of DF₂ is 0.0014%. To verify the viability of the proposed algorithm, simulation is carried out and hardware prototype is constructed. Both results show very good agreement with the theoretical prediction.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

巨型水电站孤岛试验期间AVC电压波动的解决

本文首先分析国内典型的AVC的一般配置、控制策略和控制原理,针对巨型水电站孤岛试验期间的AVC控制的复杂工况进行阐述,对出现的AVC电压波动的情况进行分析,并对采用的解决方案进行介绍,为今后类似电站的孤岛运行期间的AVC电压控制提供一些参考建议。     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

How platinum oxide affects the degradation analysis of PEM fuel cell cathodes

In this work, proton exchange membrane fuel cell cathodes are degraded with accelerated-stress-tests.These PtCo containing cathodes are analyzed at begin-of-life and end-of-test with a dedicated diagnostic procedure. For every individual load point, the oxygen transport resistance and voltage losses due to the formation of platinum oxides were obtained in addition to commonly measured electrochemical surface area, high frequency resistance, as well as cathode ionomer resistance. These data were used to break down the voltage losses into six different contributors. With this break down, performance gains and performance losses were determined at end-of-test. At low current densities, it was found that voltage losses due to degradation are dominated by the loss of specific activity and catalyst surface area - in line with the state-of-the-art knowledge. But by quantifying the losses from platinum oxide formation explicitly, we show that end-of-test an unassigned voltage loss is not only present at highest current densities, but already at low current density. More precisely, the unassigned voltage loss shows a linear increase with decreasing half cell voltage and is independent from the chosen accelerated stress test. As this unassigned loss depends on half cell voltage, it might arise from ionomer adsorption.