Modeling and simulation of single-event effect in CMOS circuit

This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device (direct ionization and indirect ionization) are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices (bipolar transistor effect, charge sharing effect) and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients (SETs) in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed.     

Design of high performance and radiation hardened SPARC-V8 processor

Design of a highly reliable SPARC-V8 processor for space applications requires consideration single-event effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose (TID). In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78×9.78 mm², and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements' experiments, which show TID resistance to 300 krad(Si), SEL immunity to greater than 92.5 MeV·cm²/mg, and an SEU error rate of 2.51×10^-4 per day.     

Radiation effects on scientific CMOS image sensor

A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to single-event latch up for LET up to110 MeV·cm²/mg.     

3GHz高速ADC陶瓷封装的电学设计

随着模数转换器(ADC)采样频率的提高,保证其电压采样精度成为封装设计中的难题。完成了一款采样频率为3 GHz的ADC陶瓷外壳的设计,根据设计规则及EDA软件仿真结果,确定ADC外壳的层叠结构及走线,使阻抗有较好的匹配性,降低信号反射;使用全波电磁场分析软件对不同材料、不同直径键合丝的传输特性进行了仿真,对关键信号放置在不同层情况下的插入损耗进行分析对比,选择符合工艺条件的最优方案。仿真结果表明该设计达到了3 GHz ADC的外壳设计要求,但实际测试结果与仿真结果有一定误差,测试用印刷电路板(PCB)的插入损耗可能是导致差异的一个重要原因。     

高压偏移栅PMOSFET击穿电压的电离辐照响应

揭示了辐照引起击穿电压变化的机制,提出了提高高压偏移栅PMOSFET击穿电压抗电离辐照的方法。对辐照后击穿电压退火特性进行了研究。     

500V高压集成电路LCH1016的研制

本文采用N阱硅栅CMOS工艺和自绝缘偏移栅高压MOS器件结构，研制出500V高压集成电路LCH1016，重点讨论了高压器件结构对击穿电压的影响及其导通电阻特性，给出了LCH1016的电路逻辑、版图设计及工艺参数控制。     

一种16位音频ΣΔA/D转换器(英文)

提出了一种16位立体声音频新型稳定的5阶ΣΔA/D转换器.该转换器由开关电容ΣΔ调制器、抽取滤波器和带隙基准电路构成.提出了一种新的稳定高阶调制器的方法和一种新的梳状滤波器.采用0.5μm5V CMOS工艺实现ΣΔA/D转换器.ΣΔA/D转换器可以得到96dB的峰值SNR,动态范围为96dB.整个芯片面积只有4.1mm×2.4mm,功耗为90mW.     

高可靠微处理器结构与实现

文章介绍了抗单粒子翻转容错处理器NBHARK的结构与实现．采用了改进的优化奇权重列编码方法纠检寄存器文件的瞬时错误。提出了多种有效方法提高整个处理器可靠性，如三模冗余内部临时寄存器,三模冗余时钟，片上EDAC，奇偶校验，强制cache缺失等。该芯片在smic0．18μmCMOS工艺投片。辐射试验表明，粒子注入（〉50，000）引起的单粒子翻转错误均成功纠正。试验采用^252Cf辐射源，3．5uCi，以及43MeV．cm^2／mg平均LET进行。     

一种高稳定性高精度低压差线性稳压器的分析与设计

提出了LDO,其基于缓慢滚降式频率补偿方法,通过在电路中引入三个极零对（极零对的产生没有增加静态功耗）,不仅克服了常规LDO不能使用低等效串联电阻、低成本陶瓷输出电容的缺点,而且确保了系统在整个负载和输入电压变化范围内稳定工作。由于LDO通常给高性能模拟电路供电,因此其输出电压精度至关重要； 而该补偿方法能满足高环路增益、高单位增益带宽的设计要求,从而大幅提高LDO的精度，该LDO基于0.5μm CMOS工艺实现，后仿结果表明,即使在低压满负载条件下,其开环DC增益仍高于70dB,满载时单位增益带宽可达3MHz,线性调整率和负载调整率分别为27μV/V和3.78μV/mA,过冲和欠冲电压均小于30mV,负载电流为150mA时的漏失电压（dropout电压）仅为120mV。