基于Chua电路的一种新型忆阻电路的混沌动力学分析

基于Chua混沌电路和三次光滑忆阻器模型,提出了一种新型忆阻混沌电路.该电路由2个电感、 2个电容、1个忆阻器和1个电阻组成.利用分岔图、Lyapunov指数、相图、Poincaré截面图和Simulink仿真对电路进行分析表明,该电路具有混沌特性.该研究结果可为混沌动力学的研究和混沌保密通信的应用提供理论参考.     

基于互补电阻开关的忆阻乘法器设计

现有的忆阻算术逻辑多采用单个忆阻器作为存储单元,在忆阻交叉阵列中易受到漏电流以及设计逻辑电路时逻辑综合复杂度高的影响,导致当前乘法器设计中串行化加法操作的延时和面积开销增加。互补电阻开关具有可重构逻辑电路的运算速度和抑制忆阻交叉阵列中漏电流的性能,是实现忆阻算术逻辑的关键器件。提出一种弱进位依赖的忆阻乘法器。为提升忆阻器的逻辑性能,基于互补电阻开关电路结构,设计两种加法器的优化方案,简化操作步骤。在此基础上,通过改进传统的乘法实现方式,并对进位数据进行拆解,降低运算过程中进位数据之间的依赖性,实现并行化的加法运算。将设计的乘法器映射到混合CMOS/crossbar结构中,乘法计算性能得到大幅提高。在Spice仿真环境下验证所提乘法器的可行性。仿真实验结果表明,与现有的乘法器相比,所提乘法器的延时开销从O(n²)降低为线性级别,同时面积开销降低约70%。     

基于忆阻器的可切换带通滤波器

将忆阻器作为射频开关,采用传统双模谐振器与改进式短路阶跃阻抗谐振器的组合结构,设计了一款 可切换的三频带通滤波器。通过合理设计忆阻器偏置电路的位置,利用忆阻器阻抗的非易失性来实现滤波器通带的可 切换功能。当滤波器工作时忆阻器处于断电的记忆状态,从而改善了可切换滤波器的互调性能。文中设计的滤波器拥 有四种可切换工作状态,包括三频、双频、单频和全阻工作模式。测试结果表明,所提出的滤波器在三频情况下各通带 的插入损耗分别是 -1. 38 dB@ 1. 75 GHz、-0. 94 dB@ 3. 10 GHz、-3. 13 dB@ 3. 70 GHz;双频工作模式下各通带的插入损 耗为-1. 67 dB@ 1. 75 GHz、-3. 10 dB@ 3. 70 GHz;单频工作模式下通带的插入损耗为-1. 35 dB@ 3. 10 GHz;全阻模式下 阻带衰减高于24. 85 dB。文中采用替代测试法进行测试,测试结果与仿真结果取得了较好的一致性。     

A memristor-based architecture combining memory and image processing

Image processing is a type of memory-access-intensive application and is applied in many fields.Logic operations are very simple ones in image processing.During these operations,memory access takes a majority of the total time consumed,which puts a great pressure on memory access speed and bandwidth.However,in traditional von Neumann architecture,memory access is the inherent bottleneck of the system;that is,the speed of memory’s data supply is far lower than the data request of processor.Memristor is considered to be the fourth circuit element after resistor,capacitor and inductor.It has the capacity of both processing and memory,which supplies a new idea for solving the"memory wall"problem.In this paper,memristor is used to build an architecture combining computing and memory,where the memory has the ability to handle some simple image processing operations.This architecture can reduce readings and writings of memory effectively,which saves memory bandwidth thus improving the efficiency of the system.Logic operations of images are considered in this paper to validate the architecture.The experimental results and theoretical analysis indicate that the architecture can reduce memory access effectively.     

一种新型双忆阻混沌系统动力学及其电路实现研究

在经典的蔡氏混沌电路基础上,引入三次非线性磁控忆阻模型,利用一个磁控忆阻模型和一个荷控忆阻模型,外加一个负电导替换变形蔡氏电路中的蔡氏二极管,设计了一个五阶混沌电路,用常规的方法研究系统的基本动力学特性。通过数值仿真结果表明电路在参数变化情况下能产生Hopf分岔和反倍周期分岔两种分岔行为,并能产生双涡卷、单涡卷、极限环、同宿轨等不同轨道,出现了双单摆运动。观察混沌吸引子推广到功率与能量信号,观察到蝴蝶翅膀重叠的奇异吸引子。通过改变初始值,能产生共存吸引子和周期极限环共存现象。为了验证电路的混沌行为,将对设计的电路进行了PSpice仿真,电路仿真结果验证了理论分析的正确性。     

基于忆阻桥效应的光纤式双光路结冰探测方法

近年来,随着防冰、除冰需求的增加,结冰探测技术受到了广泛关注,但传统的结冰传感器量程受限,且后续信号处理电路部分体积较大,难以满足应用需求.基于双光路差动测量的方法,提出一种正方形光纤束探测头分布模式和具有放大效应的忆阻桥网络结构,该网络结构通过对光电探测器的输出光电流信号进行放大,并以网络中感知忆阻器的端电压作为传感输出,从而实现冰层厚度的测量.试验仿真结果表明,该方法探测头端面的安装面积较常用圆形端面光纤束可减小约12.6%,且能够有效消除光路扰动和扩大结冰厚度的测量范围,结冰厚度的测量范围可达到38mm.     

Thermodynamic-RAM technology stack

Abstract

We introduce a technology stack or specification describing the multiple levels of abstraction and specialisation needed to implement a neuromorphic processor (NPU) based on the previously-described concept of AHaH Computing and integrate it into today’s digital computing systems. The general purpose NPU implementation described here is called Thermodynamic-RAM (kT-RAM) and is just one of many possible architectures, each with varying advantages and trade offs. Bringing us closer to brain-like neural computation, kT-RAM will provide a general-purpose adaptive hardware resource to existing computing platforms enabling fast and low-power machine learning capabilities that are currently hampered by the separation of memory and processing, a.k.a the von Neumann bottleneck. Because understanding such a processor based on non-traditional principles can be difficult, by presenting the various levels of the stack from the bottom up, layer by layer, explaining kT-RAM becomes a much easier task. The levels of the Thermodynamic-RAM technology stack include the memristor, synapse, AHaH node, kT-RAM, instruction set, sparse spike encoding, kT-RAM emulator, and SENSE server.     

A compact,low‐frequency,memristor‐based oscillator

A relaxation oscillator using a memristor is hereby presented. The memristor is used to substitute the function of a capacitor in an equivalent RC oscillator. The voltage across the memristor changes according to the quantity and polarity of the current passing through, thus substituting the changing voltage across a capacitor in the equivalent RC oscillator. The memristor has the advantage of occupying much less area than the equivalent capacitor, which may be important when trying to build on‐chip oscillators for portable or medical applications. Copyright © 2014 John Wiley & Sons, Ltd.     

A generalized family of memristor‐based voltage controlled relaxation oscillator

Recently, memristive oscillators are a significant topic in the nonlinear circuit theory where there is a possibility to build relaxation oscillators without existence of reactive elements. In this paper, a family of voltage‐controlled memristor‐based relaxation oscillator including two memristors is presented. The operation of two memristors‐based voltage relaxation oscillator circuits is demonstrated theoretically with the mathematical analysis and with numerical simulations. The generalized expressions for the oscillation frequency and conditions are derived for different cases, where a closed form is introduced for each case. The effect of changing the circuit parameters on the oscillation frequency and conditions is investigated numerically. In addition, the derived equations are verified using several transient PSPICE simulations. The power consumption of each oscillator is obtained numerically and compared with its PSPICE counterpart. Furthermore, controlling the memristive oscillator with a voltage grants the design an extra degree of freedom which increases the design flexibility. The nonlinear exponential model of memristor is employed to prove the oscillation concept. As an application, two examples of voltage‐controlled memristor‐based relaxation oscillator are provided to elaborate the effect of the reference voltage on the output voltage. This voltage‐controlled memristor‐based relaxation oscillator has nano size with storage property that makes it more efficient compared with the conventional one. It would be helpful in many communication applications.     

Current‐input current‐output analog half center oscillator and central pattern generator circuits with memristors

The comparison of the memristor to the biological synapse has motivated the introduction of memristors to biomimetic circuits such as Central Pattern Generators (CPGs) and Half Center Oscillators (HCOs). The effects of the utilization of memristors in such systems have been investigated in this work. The HCO is a neural oscillator, and the CPG is made up of 4 HCOs producing oscillations corresponding to the locomotion of a 4‐limbed animal. Analog HCO and CPG circuits have been simulated using the Cadence Virtuoso platform and effects of using current‐driven and voltage‐driven memristors in different configurations with different parameters have been analyzed. Improvement in the stability of rhythm and variations in oscillation amplitudes have been observed.