基于忆阻器的SRAM存储单元设计

为了突破冯?诺依曼架构瓶颈,实现存算一体的存储功能,利用D锁存器设计了一种忆阻器存储单元.该忆阻器存储单元由忆阻器基本逻辑与门、或门和MeMOS电路组成.PSpice仿真显示,该忆阻器存储单元不仅可以实现非易失性存储功能,而且具有体积小、功耗低、结构简单等优点,可为实现非易失性存储单元提供良好参考.     

基于AgInSbTe忆阻器的高效MLP神经网络

忆阻器自被制造出来以后在神经形态计算方面展现了巨大的应用潜力,然而众多神经形态计算算法的基于忆阻器的神经网络往往无法处理负突触权重或者需要引入非常复杂的控制电路,从而无法获得较高的处理效率.为了克服这一困难,提出一种结合忆阻器参考行和流控电压源(CCVS)的结构,实现了正负权重在单个忆阻器件上的高效映射.以双层的MLP...     

Exploiting Memristive BiFeO3 Bilayer Structures for Compact Sequential Logics

Resistive switching devices are considered as one of the most promising candidates for the next generation memories and nonvolatile logic applications. In this paper, BiFeO₃:Ti/BiFeO₃ (BFTO/BFO) bilayer structures with optimized BFTO/BFO thickness ratio which show symmetric, bipolar, and nonvolatile resistive switching with good retention and endurance performance, are presented. The resistive switching mechanism is understood by a model of flexible top and bottom Schottky‐like barrier heights in the BFTO/BFO bilayer structures. The resistive switching at both positive and negative bias make it possible to use both polarities of reading bias to simultaneously program and store all 16 Boolean logic functions into a single cell of a BFTO/BFO bilayer structure in three logic cycles.     

基于忆阻器的矩形波信号发生器

利用忆阻器独特的电路学性质,设计了一个基于忆阻器的新型矩形波信号发生器。电路中不含有分立的电容元件,输出波形频率和幅值精确可调。用PSPICE进行仿真分析,仿真结果验证了该方案的有效性。     

The Future of Memristors: Materials Engineering and Neural Networks

From Deep Blue to AlphaGo, artificial intelligence and machine learning are booming, and neural networks have become the hot research direction. However, due to the size limit of complementary metal–oxide–semiconductor (CMOS) transistors, von Neumann-based computing systems are facing multiple challenges (such as memory walls). As the number of transistors required by the neural network increases, the development of neural networks based on the von Neumann computer is limited by volume and energy consumption. As the fourth basic circuit element, memristor shines in the field of neuromorphic computing. The new computer architecture based on memristor is widely considered as a substitute for the von Neumann architecture and has great potential to deal with the neural network and big data era challenge. This article reviews existing materials and structures of memristors, neurophysiological simulations based on memristors, and applications of memristor-based neural networks. The feasibility and advancement of implementing neural networks using memristors are discussed, the difficulties that need to be overcome at this stage are put forward, and their development prospects and challenges faced are also discussed.     

Multiply accumulate operations in memristor crossbar arrays for analog computing

Memristors are now becoming a prominent candidate to serve as the building blocks of non-von Neumann inmemory computing architectures.By mapping analog numerical matrices into memristor crossbar arrays,efficient multiply accumulate operations can be performed in a massively parallel fashion using the physics mechanisms of Ohm’s law and Kirchhoff’s law.In this brief review,we present the recent progress in two niche applications:neural network accelerators and numerical computing units,mainly focusing on the advances in hardware demonstrations.The former one is regarded as soft computing since it can tolerant some degree of the device and array imperfections.The acceleration of multiple layer perceptrons,convolutional neural networks,generative adversarial networks,and long short-term memory neural networks are described.The latter one is hard computing because the solving of numerical problems requires high-precision devices.Several breakthroughs in memristive equation solvers with improved computation accuracies are highlighted.Besides,other nonvolatile devices with the capability of analog computing are also briefly introduced.Finally,we conclude the review with discussions on the challenges and opportunities for future research toward realizing memristive analog computing machines.     

基于FPGA的二值忆阻器仿真器研究及应用

基于FPGA的可重构性,提出了一种基于数字电路的二值忆阻器仿真器。与模拟电路忆阻器仿真器相比,所提出基于数字电路的忆阻器仿真器易于重新配置,与它所基于的数学模型表现出很好的匹配性,符合忆阻器仿真器所有要求的特点。实现了基于该仿真器的与门、或门、加法器及三人表决器。使用Altera Quartus II和ModelSim工具对仿真器功能和基于该仿真器实现的逻辑电路进行验证。给出所有设计电路的原理图、仿真结果和FPGA资源消耗。仿真结果表明,该二值忆阻器仿真器相比其他数字电路忆阻器仿真器具有更少的硬件资源消耗,更适合用于大规模忆阻器阵列研究。     

忆阻-CMOS混合模逆电路设计

模逆运算是加密算法中最复杂的运算,更是最关键的模块之一。忆阻器是替代现有的晶体管从而延续摩尔定律的有力竞争者。文中结合信息安全和忆阻器两个领域的研究现状,将忆阻蕴含机制应用于模逆电路设计,研究忆阻器应用于大规模数字电路中的可行性和适应性。首先,基于FPGA平台提出忆阻蕴含逻辑电路模型,进而实现了基础逻辑门和加法器等功能模块;再调用功能模块,成功设计出了基于二进制扩展的Euclidean算法的忆阻-CMOS混合模逆电路。经仿真与验证,模逆模块在200MHz的时钟下能正确地执行设计功能。     

气体放电灯的电路特性

工作状态下的气体放电灯,通常认为具有电阻电感特性(R-L),但是随着电路理论的发展以及气体放电灯的广泛应用,根据它的工作原理及电路特性,我们认为用现有的R、L、C以及它们的组合来表示它的电路特性是不合适的。本文从电路理论以及大量的实验结果说明了这个问题,并认为气体放电灯的电路特性应该用“流控忆阻器”来表征。正确认识气体放电灯的电路特性,对制灯工业及镇流器的设计、生产和发展都有指导意义,对气体放电灯也将出现一系列新的更合理的计算方法。     

基于改进忆阻器的高通滤波器设计与仿真

针对传统的忆阻器模型存在不能很好地与HP实验室提出的忆阻器物理模型中忆阻器的阻值变化特点相符的问题,提出了一种改进的带有阈值电压的忆阻器模型,该模型能很好地模拟忆阻器的"激活"现象,其特性与HP实验室的忆阻器物理模型相符;基于该改进模型设计了一种高通滤波器电路,该电路通过改变忆阻器阻值控制电路的输出信号来改变忆阻器的阻值,从而实现了滤波器截止频率的调节。SPICE仿真结果验证了设计的正确性。