Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

一种消除反馈延迟的全数字锁相环

针对传统数字锁相环存在的反馈滞后造成系统动、静态性能退化的问题,提出一种消除反馈滞后一拍的方法,以无反馈滞后理想数字锁相环为参考模型,利用数字锁相环当前输出与上一时刻输出,计算得到与理想数字锁相环一致的结果,从而消除反馈滞后一拍。所提出的锁相环仅以两个乘法器的额外开销即可大幅增强锁相环的稳定性,并且使在s域内设计的性能指标能够在z域内严格实现,克服了传统数字锁相环性能退化的问题。仿真和实验结果表明,所提改进的数字锁相环阶跃响应和频率特性均与理想数字锁相环一致,显著提高了锁相环性能,所提新算法增加的计算量较少,具有较大的实际应用价值。     

Robust stability analysis and improved design of phase‐locked loops with non‐monotonic nonlinearities: LMI‐based approach

Due to nonlinear nature of several phase detectors, linear approximation method often leads to performance degradation in many phase‐locked loops (PLLs), particularly when the phase errors are sufficiently large. A third or higher order PLL, in spite of the ability to track a wider variety of inputs and having higher operating‐frequency range, requires more design attention in order to ensure stable tracking. In this work, with the nonlinearities inserted into the system's model, suitable criteria that take into account the nonlinearities' non‐monotonicity, sector and slope bounds are employed to establish robust stability conditions. The result is applicable to any PLLs without order and type restrictions. For Type‐1 PLLs, the resulting condition can be used to search for the maximum stable loop gain, which is also linked to the lock‐in range of the system. In the later part of this work, the focus is devoted towards designing PLLs with high lock‐in range, which is performed via mixing the proposed method with H _∞ synthesis. The searches for the parameters in both PLL analysis and design are expressed in terms of convex linear matrix inequalities, which are computationally tractable. To illustrate the improvement introduced via this approach, several numerical examples and simulations are included with comparisons over conventional methods. Copyright © 2017John Wiley & Sons, Ltd.     

基于ARM的通用型励磁控制器设计

针对移动电站电源制式的多样化,设计了一种以STM32F103ZET为控制核心的同步电机通用型励磁控制系统,设计了低剩磁电压起励电路,满足了不同剩磁条件下的起励要求;针对独立电力系统的电压、频率波动较大造成采集精度下降的问题,引入了锁相环电路,实现了同步采样,提高了采样精度;采用参数自整定模糊PID的控制策略,通过IGBT功率器件进行励磁电压的PWM调节。实验结果表明,可以满足通用化的要求,具有较好的动、静态性能,调节速度快,完全符合规定的性能指标。     

MEMS谐振器刚度非线性特性及其表征

为了准确表征微电子机械系统(MEMS)谐振器在大振幅运动时的行为特性,建立了刚度非线性MEMS谐振器集总参数模型,并创建了一整套MEMS谐振器非线性特性的表征方法和测试系统。搭建了基于锁相环和自动增益控制的MEMS谐振器闭环工作电路,分析了不同驱动振幅下,MEMS谐振器的工作状态。推导建立了工作振幅、工作频率与MEMS谐振器刚度非线性之间的数量关系。最后,基于衰减模式和稳定振荡模式两种工作形态,实际测量了MEMS谐振器的无阻尼自然谐振频率和刚度非线性。结果显示:无阻尼自然谐振频率和刚度非线性系数的测量重复性分别为18.6×10-6和1.50%。针对实测的MEMS谐振器无激励振幅自衰减曲线,分别用理想二阶系统谐振器模型和刚度非线性谐振器模型进行残差分析。结果显示后者的残差要比前者的残差小9.5%,表明刚度非线性MEMS谐振器模型更接近真实情况,也验证了该刚度非线性特性表征方法的准确性。基于该方法,测量了MEMS谐振器刚度非线性系数和无阻尼自然谐振频率的温度特性,得到的无阻尼自然谐振频率的温度系数为-0.487Hz/℃,线性拟合度达99.964%。     

一种新型SPMSM无位置传感器驱动系统研究

针对表贴式永磁同步电机(SPMSM),提出了一种基于新型反电动势观测器的无位置传感器驱动系统控制方案。为了实现无传感器控制,该系统在传统反电动势观测器的基础上进行了一定的改进,并引入锁相环(PLL)来确保估算器能够快速、准确地获取转子位置信息和转速信息,从而实现电机的转子磁场定向及转速调节。建立了系统数学模型、控制系统结构框架,并且对该速度/位置估算器原理进行了理论分析及Matlab仿真验证。最后,基于TMS320F2808的永磁同步电机实验平台进行了相关实验,实验结果验证了该控制算法具有调速范围宽、动态响应快、带载能力强及系统可行性、实用性强等特点。     

一种针对压缩域信号的新型锁相环技术

针对通信信号压缩采样获得的压缩域信号频率、相位提取问题,提出了一种基于压缩感知的新型锁相环技术。通过深入研究压缩域的信号估计问题,提出了压缩域锁相环路,可以直接在压缩域同步跟踪信号频率和相位变化,不再需要高复杂度的信号重构处理。分析了环路模型及其估计性能,并针对该锁相环可行性和性能分别进行了仿真实验。仿真结果不仅验证了压缩域锁相环的可行性,同时表明该环路能够实现高动态信号的高精度频率提取。压缩域锁相环的应用潜力较大,例如可以作为压缩感知通信接收机的同步解调方法。     

A low phase noise and low spur PLL with auto frequency control circuit for L1-band GPS receiver

A low phase noise and low spur phase-locked loop (PLL) for L1-band global positioning system receiver is proposed in this paper. For obtaining low phase noise for PLL, All-PMOS LC-VCO with varactor-smoothing technique and noise-filtering technique is adopted. To reduce the reference spur, a low current-mismatch charge pump is carefully designed. A quasi-closed-loop auto frequency control circuit is used to accelerate the lock process of PLL. The PLL is fabricated in 180 nm CMOS Mixed-Signal process while it operates under 1.8 V supply voltage. The measured output frequency of PLL is 1.571 GHz and output power is −1.418 dBm. The in-band phase noise is −98.1 dBc/Hz @ 100 kHz, while the out-band phase noise is −130.3 dBc/Hz @ 1 MHz. The reference spur is −75.8 dBc at 16.368 MHz offset. When quasi closed-loop AFC is working, the measured lock time is about 10.2 μs.     

高帧率步进频穿墙成像雷达扫频方法

步进频是穿墙成像雷达的常用波形,传统采用锁相合成技术的步进频穿墙成像雷达的跳频时间长,帧率很低,难以满足穿墙雷达实时成像的要求。为了解决这个问题,提出了一种新的扫描方案,可以通过现场可编程门阵列（FPGA）实现对扫描方式的可调控制,在不影响回波波形及成像效果的情况下显著提高了步进频穿墙成像雷达的帧率。在2 MHz的频率步长以及2.5 GHz的频段范围内时,实际成像帧率可以达到14 Hz,在一定程度上满足了实时成像的要求。试验测试结果验证了所提方法的可行性。     

基于DDS与PLL的C波段全相参雷达频综设计

提出了一种直接数字频率合成(DDS)与锁相环(PLL)相结合的全相参频率合成方案。运用HMC704控制压控振荡器(VCO)设计高性能锁相本振源,将AD9910在基带产生的线性调频(LFM)脉冲调制信号经二次变频搬移到C波段,改善了输出信号的相噪和杂散,降低了系统的复杂性。实现了低相噪,低杂散,窄步进的C波段全相参雷达频综。结果表明,该频综在C波段输出LFM信号的幅度大于10dBm,频率步进为1kHz,相位噪声优于-103dBc/Hz@1kHz,各项指标均满足实际工程要求。