Efficient design of magnitude and 2's complement comparators

Digital comparators are important arithmetic components used in digital systems to determine if two numbers are equal, or if one number is greater or less than the other. In this work, the design of magnitude and 2's complement comparators is examined. New OR-based full tree and simplified tree magnitude comparator architectures are proposed. The existing and the proposed comparator architectures are implemented in standard cell technology and evaluated, after extensive experimental analysis, in high performance and relaxed conditions. The proposed comparators operate faster than the existing ones, while operating at the same speed yield significant improvement in area complexity and power dissipation.     

采动建筑物在沉陷区内位置的GIS拓扑算法

地下资源开采常常引起周围环境的负面效应,造成地面建筑物、公用地下管线和各种地下设施以及城市道路的路基、路面、铁路等不同程度的损害,利用GIS可以有效地把这种负面效应和损害可视化.在可视化过程中,经常要判断不同地理要素的空间位置关系.基于GIS所特有的拓扑关系特性,把开采沉陷区域的建筑物和沉陷等值线空间位置关系抽象成理论模型,并进一步探讨了点与曲线环关系算法以及利用现有GIS软件如何来实现拓扑关系的方法.通过这种可视化,可以为决策提供可靠的信息依据,从而更好地为工程服务.     

全光纤电流互感器PID控制算法研究

全光纤电流互感器（FOCT）克服了传统电磁式电流互感器在暂态响应方面的弱点,优化动态特性有助于提高全光纤电流互感器保护动作的快速性。全光纤电流互感器的检测电路的带宽限制了系统的闭环带宽。对于采用数字闭环方案的全光纤电流互感器,其带宽限制主要由闭环数字控制算法决定。通过理论分析、仿真及实验验证,表明在闭环控制算法中引入PID控制算法,有效提高了闭环带宽,为全光纤电流互感器在智能电网保护中的推广应用具有重要的意义。     

数字化变电站过程层通信故障发生装置

设计了一种用于继电保护测试的数字化变电站过程层通信故障发生装置。以EP3C25现场可编程门阵列芯片为中央控制器,以88E1111 k M以太网物理层芯片为通信接口,通过"截取-修改-转发"方式人为地改变过程层网络中的采样值报文和GOOSE报文,使继电保护装置接受的信号出现异常。在此基础上,采用信息熵检测法监视电压信息的变化,实现过程层通信故障、电力系统故障的联合仿真。实验表明,通信故障发生装置引起的网络延时很短,对RTDS模拟的绝大部分电力系统故障能够有效鉴别。     

基于图像处理的海面动目标DP 相参检测方法

海面动目标检测是对海搜索雷达的一种重要工作模式,由于受海杂波影响,采用常规的非相参处理检测动目标时效果不佳。文中提出了一种基于图像处理的低重复频率DP 相参检测动目标的方法。该方法利用图像分割提取技术,针对二维频谱图运用sobel 算子提取边界,将杂波区和清晰区精确分开,提高了海面动目标的检测能力,并通过实测数据证明了该方法有效性和可实现性。     

Flexible Prime‐Field Genus 2 Hyperelliptic Curve Cryptography Processor with Low Power Consumption and Uniform Power Draw

This paper presents an energy‐efficient (low power) prime‐field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a 0.13 μm standard CMOS technology, performs an 81‐bit divisor multiplication in 503 ms consuming only 6.55 μJ of energy (average power consumption is 12.76 μW). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.     

基于共轭算法的弹道修正方法

研究一种在空间3-D中求解弹道修正的最优控制问题的方法。根据Pontryagin极小值原理,将弹道修问题被转换成两点边值问题(Two-Point Boundary Value Problem,TPBVP),利用给定的边界条件,可将TPBVP可转换成针对主导向量初始值的参数优化问题,并采用共轭算法求解主导向量初值。采用该控制方法进行了仿真实验以证明其可行性及准确性,仿真实验数据表明:所提出的算法鲁棒性强、精度高,可以满足战术需要。     

Methods for uncertainty propagation in life cycle assessment

Life cycle assessment (LCA) calculates the environmental impact of a product over its entire life cycle. Uncertainty analysis is an important aspect in LCA, and is usually performed using Monte Carlo sampling. In this study, Monte Carlo sampling, Latin hypercube sampling, quasi Monte Carlo sampling, analytical uncertainty propagation and fuzzy interval arithmetic were compared based on e.g. convergence rate and output statistics. Each method was tested on three LCA case studies, which differed in size and behaviour. Uncertainty propagation in LCA using a sampling method leads to more (directly) usable information compared to fuzzy interval arithmetic or analytical uncertainty propagation. Latin hypercube and quasi Monte Carlo sampling provide more accuracy in determining the sample mean than Monte Carlo sampling and can even converge faster than Monte Carlo sampling for some of the case studies discussed in this paper.     

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

In this paper, we have analyzed the register complexity of direct-form and transpose-form structures of FIR filter and explored the possibility of register reuse. We find that direct-form structure involves significantly less registers than the transpose-form structure, and it allows register reuse in parallel implementation. We analyze further the LUT consumption and other resources of DA-based parallel FIR filter structures, and find that the input delay unit, coefficient storage unit and partial product generation unit are also shared besides LUT words when multiple filter outputs are computed in parallel. Based on these finding, we propose a design approach, and used that to derive a DA-based architecture for reconfigurable block-based FIR filter, which is scalable for larger block-sizes and higher filter-lengths. Interestingly, the number of registers of the proposed structure does not increase proportionately with the block-size. This is a major advantage for area-delay and energy efficient high-throughput implementation of reconfigurable FIR filters of higher block-sizes. Theoretical comparison shows that the proposed structure for block-size 8 and filter-length 64 involves 60% more flip-flops, 6.2 times more adders, 3.5 times more AND-OR gates, and offers 8 times higher throughput. ASIC synthesis result shows that the proposed structure for block-size 8 and filter-length 64 involves 1.8 times less area-delay product (ADP) and energy per sample (EPS) than the existing design, and it can support 8 times higher throughput. The proposed structure for block sizes 4 and 8, respectively, consumes 38% and 50% less power than the exiting structure for the same throughput rates on average for different supply voltages.