一款0.16 mm2基于180 nm CMOS采用全局去偏斜的半速率8×2.5 Gb/s时钟转发架构接收机

在时钟转发架构的高速有线通信接收机中,需要去偏斜电路实现时钟与数据之间的最佳采样关系,并保证多路数据的同步。本文提出了一种全局去偏斜方案,仅采用一路数据与时钟进行对齐,并通过时钟延时匹配与分布技术实现多路数据同步,减小了各通道独立去偏斜方案带来的功耗与面积开销。所提出的接收机由8路数据通道、1路半速率转发时钟通道与基于延迟锁定环路的全局去偏斜电路构成。基于180 nm CMOS工艺,在2.5 Gb/s数据率下,可去除输入时钟与数据任意偏斜,得到位于数据中心的采样相位,同时具有时钟占空比校准能力。在1.8 V电源电压下,所提出的接收机总功耗为187 mW,总面积为0.16 mm²,对比各通道独立去偏斜方案,功耗和面积开销分别节约了45.2%与62.8%。     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

A 14-bit 40-MHz analog front end for CCD application

A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8×4.8 mm² and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit.     

一种10位50MS/s两级逐次逼近流水线混合型A/D转换器

本文在0.18μm CMOS工艺下,实现了一款10位50MS/s两级逐次逼近流水线混合型模数转换器（pipeline SAR ADC）。其由基于逐次逼近的增益模数单元和逐次逼近ADC组成,并采用1位冗余位放宽了子模数转换器的比较误差。通过采用逐次逼近结构,增益减半MDAC技术,动态比较器及动态逐次逼近控制逻辑,降低了模数转换器的功耗和面积。流片测试结果表明,在1.8V电源电压,50MS/s采样速率下,信噪失真比(SFDR)和功耗分别为56.04dB和5mV。     

一款400μm2用于极短距离接收机具有中频补偿的56 Gb/s PAM4反相器型连续时间线性均衡器

高速极短距离有线数据接口是芯粒间互连的重要技术方案。传统的基于电流模逻辑的连续时间线性均衡器由于高电源电压和无源器件的使用已经无法满足芯粒间数据接口高密度、小型化、低功耗的需求。针对该问题,本文提出了一种带中频补偿的反相器型连续时间线性均衡器,可在极短距离应用中传输28 Gb/s非归零信号以及56 Gb/s四电平脉冲幅度调制信号。本设计采用28 nm CMOS工艺实现,核心面积仅为400μm²。经过-9.4 dB@14 GHz的极短距离信道后,基于版图的仿真结果表明,所提出的连续时间线性均衡器使28 Gbaud的非归零信号与四电平脉冲幅度调制信号眼宽分别提升0.14 UI与0.41 UI,眼高提升328 mV与119 mV,56 Gb/s四电平脉冲幅度调制信号工况下功耗为6.12 mW。     

一种光接收机中的高增益宽动态范围跨阻放大器

As the front-end preamplifiers in optical receivers, transimpedance amplifiers （TIAs） are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range （DR） to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the -3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the -3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage.     

用于流水线ADC的频率自适应可编程MDAC电路

A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.     

一种具有延迟校准功能的可编程多相位时钟电路

基于延迟锁相环原理,提出了一种新型的具有延迟校准功能的可编程多相位时钟电路,能为工作在80MHz的电荷耦合器件信号处理器提供精度高达390ps的时序信号．将主时钟的单周期等分为32份,通过可编程相位组合电路,产生相位及占空比可调的信号,能满足不同电荷耦合器件所需的最优工作时序．传统的延迟锁相环结构随着延迟单元的增加,延迟单元之间不匹配愈加明显,导致输出相位偏离理想位置．引入延迟校准电路可以显著降低相位之间的误差,校准后的多相位时钟信号接入可编程相位组合器进行选择组合,产生所需的高精度时序信号．基于SMIC 0.18μm 3.3V CMOS工艺完成设计,在80MHz主时钟下的后仿真结果表明：电路可产生占空比范围为2％～98％的输出时钟,校准后的延迟误差小于5ps,边到边抖动为 1.14ps,有效地保证了相位精度．