A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.     

一种应用于调频接收机，功耗为2.52mW，具有72dB动态范围的连续时间ΔΣ调制器

本文提出一个采用三阶滤波器,三位量化器的连续时间ΔΣ 调制器。该调制器对环路延迟,时钟抖动,以及RC时间常数变化具有鲁棒性。在积分器设计中,采用了增益带宽积扩展结构的运放,提高了滤波器的线性度。该芯片使用130nmCMOS工艺设计,可以应用在调频接收机中。测试结果表明,在带宽为500 kHz,时钟为26MHz条件下,该调制器实现了72dB的动态范围和70.7dB的信噪失真比,在1.2V电压下消耗2.52mW功耗。     

用于WLAN接收机的流水线A/D转换器设计

为一款支持802.11a/b/g协议的WIAN芯片设计了接收机内部的流水线A/D转换器.采用运放共享技术,减少了一半的运算放大器,节省了芯片面积,并降低了功耗.该A/D转换器采样速率为40 MHZ,设计精度为10位,使用HJTC 0.18μm 1P6M CMOS工艺流片并测试成功,当输入频率为1 MHz、无杂散动态范围为61.43 dB的正弦信号时,测得输出数字信号的无杂散动态范围为58.6 dB,信号与噪声谐波失真比为52.87 dB,有效位数为8.49位.