Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis

Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm².     

Visual odometry based on the Fourier transform using a monocular ground-facing camera

This paper presents a visual odometry method that estimates the location and orientation of a robot. The visual odometry approach is based on the Fourier transform, which extracts the translation between consecutive image’s regions captured using a ground-facing camera. The proposed method is especially suited if no distinct visual features are present on the ground. This approach is resistant to wheel slippage because it is independent of the kinematics of the vehicle. The method has been tested on different experimental platforms and evaluated against the ground truth, including a successful loop-closing test, to demonstrate its general use and performance.     

Mpeg2 Video Encoding in Consumer Electronics

Only very recently, single-chip MPEG2 video encoders are being reported. They are a result of additional interest in encoding in consumer products, apart from broadcast encoding, where a video encoder contains several expensive chips. Only single-chip solutions are cost-effective enough to enable digital recording for the consumer. The professional broadcast encoders are expensive because they use the full MPEG toolkit to guarantee good image quality, at the lowest possible bit-rate. Some MPEG tools are costly in hardware and these are therefore not feasible in single-chip solutions. This results in higher bit-rates, that can be accepted because of the available channel and storage capacity of the latest consumer storage media, harddisk, digital tape (D-VHS) and Digital Versatile Disk (DVD). A consumer product is I.McIC, a single-chip MPEG2 video encoder. It operates in ML@SP mode which can be decoded by all MPEG2 decoders. The IC is highly-integrated, as it contains motion-estimation and compensation, adaptive temporal noise filtering and buffer/bit-rate control. The high-throughput functions of the MPEG algorithm are mapped onto pipelined dedicated hardware, whereas the remaining functions are processed by an application-specific instruction-set processor. Software for this processor can be downloaded, in order to suit the IC for different applications and operating conditions. The IC consists of several communicating processors which were designed using high-level synthesis tools, PHIDEO and DSP Station.     

Noise reduction of image sequences using motion compensation andsignal decomposition

In this paper, a new spatio-temporal filtering method for removing noise from image sequences is proposed. This method combines the use of motion compensation and signal decomposition to account for the effects of object motion. Because of object motion, image sequences are temporally nonstationary, which requires the use of adaptive filters. By motion compensating the sequence prior to filtering, nonstationarities, i.e., parts of the signal that are momentarily not stationary, can be reduced significantly. However, since not all nonstationarities can be accounted for by motion, a motion-compensated signal still contains nonstationarities. An adaptive algorithm based on order statistics is described that decomposes the motion-compensated signal into a noise-free nonstationary part and a noisy stationary part. An RLS filter is then used to filter the noise from the stationary signal. Our new method is experimentally compared with various noise filtering approaches from literature.     

An adaptive order-statistic noise filter for gamma-corrected imagesequences

Original video signals are often corrupted by a certain amount of noise originating from the camera electronics. As a result of the gamma correction in cameras, the observed noise is signal dependent. We present a spatio-temporal order-statistic (OS) noise filter that takes into account the gamma correction in the camera. The calculation of the filter coefficients requires higher-order order-statistics (HOOS) of the noise process. We make use of a range test (RT) to determine locally from which neighboring signal values an estimate should be formed. The noise filter that we arrive at is adaptive and computationally efficient.     

Power Consumption of Fault Tolerant Busses

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.     

I.McIC: a single-chip MPEG-2 video encoder for storage

I.McIC is a single-chip MPEG-2 video encoder for consumer storage applications. It supports both intra- and inter-coding mode to achieve bit rates from 5-15 Mb/s. It contains a recursive motion estimator, a programmable buffer/bit-rate controller, and a temporal noise-reduction stage. The resulting IC has 4.5×10⁶ transistors and measures 192 mm² in a 0.5-μm process. I.McIC was designed using mainly high-level synthesis tools. High-throughput fixed MPEG functions are performed by dedicated hardware. The remainder is performed in software by an embedded application-specific instruction-set processor with downloadable microcode to suit the IC for different applications of video coding     

IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors

Fault tolerant design is a technique emerging in Integrated Circuits (ICs) to deal with the increasing error susceptibility (Soft Errors, Single Event Upsets, (SEUs)) caused by e.g. alpha particles. A side effect of these methods is that they also compensate for manufacturing defects, thereby increasing the yield and lowering the production cost in certain conditions. In this paper, it is shown that increasing the IC area (by applying fault tolerant design techniques for SEUs) leads to a synergistic advantage under certain conditions: lower production costs because of a better yield. To guide designers in deciding when the fault tolerant techniques are beneficial, break-even points between fault tolerant and regular designs are presented as function of IC area, fault tolerant overhead and defect density.